library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity AD_CONV is
port(
Data0 : out std_logic_vector(7 downto 0);
clk : in std_logic;
CS : out std_logic;
DI : out std_logic;
DO : in std_logic;
C_CLK : out std_logic
);
end entity;
architecture bhv of AD_CONV is
type states is (st0,st1,st2,st3,st4,st5,st6,st7,st8,st9,st10,st11,st12);
signal current_state,next_state : states := st0;
signal DigData : std_logic_vector(8 downto 0);
signal lock : std_logic;
signal count : integer := 8;
begin
process(current_state)
begin
case current_state is
when st0 => CS <= '0';
lock <= '0';
C_CLK <= '1';
DI <= '1'; --start chip
next_state <= st1;
when st1 => CS <= '0';
lock <= '0';
DI <= '1'; --start chip
C_CLK <= '1';
next_state <= st2;
when st2 => CS <= '0';
lock <= '0';
C_CLK <= '0';
next_state <= st3;
when st3 => CS <= '0';
lock <= '0';
DI <= '1'; --select ch0
C_CLK <= '1';
next_state <= st4;
when st4 => CS <= '0';
lock <= '0';
C_CLK <= '0';
next_state <= st5;
when st5 => CS <= '0';
lock <= '0'; --select ch0
DI <= '0';
C_CLK <= '1';
next_state <= st6;
when st6 => CS <= '0';
lock <= '0';
C_CLK <= '0';
next_state <= st7;
when st7 => CS <= '0';
lock <= '0';
C_CLK <= '1';
next_state <= st8;
when st8 => CS <= '0'; --start Conv 7
lock <= '0';
DigData(count) <= DO;
count <= count - 1;
C_CLK <= '0';
next_state <= st9;
when st9 => CS <= '0';
lock <= '0';
C_CLK <= '1';
next_state <= st10;
when st10 => CS <= '0';
lock <= '0';
if(count = 0) then
count <= 8;
CS <= '1';
next_state <= st11;
else
C_CLK <= '1';
next_state <= st8;
end if;
when st11 => CS <= '1';
lock <= '1';
next_state <= st12;
when st12 => CS <= '0';
next_state <= st0;
when others => next_state <= st0;CS <= '0';
end case;
end process;
process(clk)
variable clk_count : integer := 0;
begin
if(clk'event and clk = '1') then
clk_count := clk_count + 1;
if clk_count >= 400 then
clk_count := 0;
current_state <= next_state;
end if;
end if;
end process;
process(lock)
begin
if (lock = '1' and lock'event) then
Data0(7 downto 0) <= DigData(8 downto 1);
end if;
end process;
end architecture;
...
Warning: Latch AD_CONV:inst|count[10] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal AD_CONV:inst|current_state.st10
Warning: Latch AD_CONV:inst|count[11] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal AD_CONV:inst|current_state.st10
...
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