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为什么我的仿真结果有延迟？

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mux2s1 is
port ( a, b, s : in std_logic;
             y : out std_logic
);
end entity mux2s1;
architecture behav of mux2s1 is
signal q : std_logic;
begin
process(a,b,s)
begin
if s='1' then q<=a;
else q<=b;
end if;
y<=q;
end process;
end architecture;