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Verilog HDL 程序举例--测试向量（Test Bench）和波形发生器：

----------------------------------------------------------------------------------
--
-- 采用ROM结构的8bit采样 sine波形发生器
--
-- Download from http://www.pld.com.cn
-- The data for each signal shape is stored in a separate memory block.
-- NOTE: At least two samples per the highest output signal frequency are required to produce a valid waveform.
-- The contents of the ROM is synchronously sent to the output in accordance with the selected frequency and phase shift.
-- The following table shows how to configure the phase shift and signal frequency.
--
-- PR FR DATA Description
-- 1 0 programming phase shift
-- 0 1 programming work frequency
--
--
-- FR: Specifies how many CLK cycles per a single analog waveform sample are required.

-----------------------------------------------------------------------------------



------------------------------------------------------------------------------------
-- DESCRIPTION : Cascadable Accumulator with Adder
-- Width : 6
-- CLK (CLK) active : high
-- CLR (CLR) active : high
-- CLR (CLR) type : asynchronous
-- CE (CE) active : high
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_acc6 is
port (
CLK : in std_logic;
CE : in std_logic;
CLR : in std_logic;
A : in std_logic_vector (5 downto 0);
Q : out std_logic_vector (5 downto 0)
);
end entity;



architecture acc_arch of generator_acc6 is
signal REG_Q : std_logic_vector (5 downto 0);
signal TEMP_Q : std_logic_vector (5 downto 0);
begin

process (REG_Q, A)
begin
TEMP_Q <= REG_Q + A;
end process;

process(CLK, CLR)
begin
if CLR = '1' then
REG_Q <= "000000";
elsif rising_edge(CLK) then
if CE = '1' then
REG_Q <= TEMP_Q;
end if;
end if;
end process;

Q <= REG_Q;


end architecture;


------------------------------------------------------------------------------------
-- DESCRIPTION : Multiplexer
-- Code style: used case statement
-- Width of output terminal: 8
-- Number of terminals: 1
-- Output value of all bits when enable not active: '0'
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator_mux is
port (
I0 : in std_logic_vector (7 downto 0);
S : in std_logic;
O : out std_logic_vector (7 downto 0)
);
end entity;



architecture mux_arch of generator_mux is
begin

process (S, I0)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;

end architecture;

------------------------------------------------------------------------------------
-- DESCRIPTION : cascadable Adder
-- Width: 6
--
--
------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity generator_adder is
port (
A, B : in std_logic_vector (5 downto 0);
Q : out std_logic_vector (5 downto 0)
);
end entity;

--}} End of automatically maintained section

architecture add_anGen_arch of generator_adder is
begin

process (A, B)
begin
Q <= A + B;
end process;

end architecture add_anGen_arch;

------------------------------------------------------------------------------------
-- DESCRIPTION : Gate: AND
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity generator_and2 is
port (
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
O : out STD_LOGIC
);
end entity;



architecture and_anGen_arch of generator_and2 is
begin
O <= I0 and I1;
end architecture and_anGen_arch;

------------------------------------------------------------------------------------
-- DESCRIPTION : Name : Analog Generator ROM
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity generator_sin is
port (
OE : in STD_LOGIC;
ADDRESS : in STD_LOGIC_VECTOR(5 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0) );

end generator_sin;



architecture sin_arch of generator_sin is

begin
process(ADDRESS, OE)
begin
if (OE = '1') then
case (ADDRESS) is
when "000000" => Q <= CONV_STD_LOGIC_VECTOR(0,8);
when "000001" => Q <= CONV_STD_LOGIC_VECTOR(1,8);
when "000010" => Q <= CONV_STD_LOGIC_VECTOR(3,8);
when "000011" => Q <= CONV_STD_LOGIC_VECTOR(5,8);
when "000100" => Q <= CONV_STD_LOGIC_VECTOR(7,8);
when "000101" => Q <= CONV_STD_LOGIC_VECTOR(10,8);
when "000110" => Q <= CONV_STD_LOGIC_VECTOR(13,8);
when "000111" => Q <= CONV_STD_LOGIC_VECTOR(17,8);
when "001000" => Q <= CONV_STD_LOGIC_VECTOR(21,8);
when "001001" => Q <= CONV_STD_LOGIC_VECTOR(25,8);
when "001010" => Q <= CONV_STD_LOGIC_VECTOR(31,8);
when "001011" => Q <= CONV_STD_LOGIC_VECTOR(37,8);
when "001100" => Q <= CONV_STD_LOGIC_VECTOR(43,8);
when "001101" => Q <= CONV_STD_LOGIC_VECTOR(51,8);
when "001110" => Q <= CONV_STD_LOGIC_VECTOR(60,8);
when "001111" => Q <= CONV_STD_LOGIC_VECTOR(72,8);
when "010000" => Q <= CONV_STD_LOGIC_VECTOR(85,8);
when "010001" => Q <= CONV_STD_LOGIC_VECTOR(100,8);
when "010010" => Q <= CONV_STD_LOGIC_VECTOR(116,8);
when "010011" => Q <= CONV_STD_LOGIC_VECTOR(132,8);
when "010100" => Q <= CONV_STD_LOGIC_VECTOR(148,8);
when "010101" => Q <= CONV_STD_LOGIC_VECTOR(164,8);
when "010110" => Q <= CONV_STD_LOGIC_VECTOR(180,8);
when "010111" => Q <= CONV_STD_LOGIC_VECTOR(196,8);
when "011000" => Q <= CONV_STD_LOGIC_VECTOR(212,8);
when "011001" => Q <= CONV_STD_LOGIC_VECTOR(228,8);
when "011010" => Q <= CONV_STD_LOGIC_VECTOR(234,8);
when "011011" => Q <= CONV_STD_LOGIC_VECTOR(238,8);
when "011100" => Q <= CONV_STD_LOGIC_VECTOR(244,8);
when "011101" => Q <= CONV_STD_LOGIC_VECTOR(248,8);
when "011110" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
when "011111" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
when "100000" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
when "100001" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
when "100010" => Q <= CONV_STD_LOGIC_VECTOR(255,8);
when "100011" => Q <= CONV_STD_LOGIC_VECTOR(248,8);
when "100100" => Q <= CONV_STD_LOGIC_VECTOR(244,8);
when "100101" => Q <= CONV_STD_LOGIC_VECTOR(238,8);
when "100110" => Q <= CONV_STD_LOGIC_VECTOR(234,8);
when "100111" => Q <= CONV_STD_LOGIC_VECTOR(228,8);
when "101000" => Q <= CONV_STD_LOGIC_VECTOR(212,8);
when "101001" => Q <= CONV_STD_LOGIC_VECTOR(196,8);
when "101010" => Q <= CONV_STD_LOGIC_VECTOR(180,8);
when "101011" => Q <= CONV_STD_LOGIC_VECTOR(164,8);
when "101100" => Q <= CONV_STD_LOGIC_VECTOR(148,8);
when "101101" => Q <= CONV_STD_LOGIC_VECTOR(132,8);
when "101110" => Q <= CONV_STD_LOGIC_VECTOR(116,8);
when "101111" => Q <= CONV_STD_LOGIC_VECTOR(100,8);
when "110000" => Q <= CONV_STD_LOGIC_VECTOR(85,8);
when "110001" => Q <= CONV_STD_LOGIC_VECTOR(72,8);
when "110010" => Q <= CONV_STD_LOGIC_VECTOR(60,8);
when "110011" => Q <= CONV_STD_LOGIC_VECTOR(51,8);
when "110100" => Q <= CONV_STD_LOGIC_VECTOR(43,8);
when "110101" => Q <= CONV_STD_LOGIC_VECTOR(37,8);
when "110110" => Q <= CONV_STD_LOGIC_VECTOR(31,8);
when "110111" => Q <= CONV_STD_LOGIC_VECTOR(25,8);
when "111000" => Q <= CONV_STD_LOGIC_VECTOR(21,8);
when "111001" => Q <= CONV_STD_LOGIC_VECTOR(17,8);
when "111010" => Q <= CONV_STD_LOGIC_VECTOR(13,8);
when "111011" => Q <= CONV_STD_LOGIC_VECTOR(10,8);
when "111100" => Q <= CONV_STD_LOGIC_VECTOR(7,8);
when "111101" => Q <= CONV_STD_LOGIC_VECTOR(5,8);
when "111110" => Q <= CONV_STD_LOGIC_VECTOR(3,8);
when "111111" => Q <= CONV_STD_LOGIC_VECTOR(0,8);
when others => Q <= "00000000";
end case;
else
Q <= "ZZZZZZZZ";
end if;
end process;
end architecture sin_arch;

------------------------------------------------------------------------------------
-- DESCRIPTION : Flip-flop D type
-- Width: 6
-- Clock active: high
-- Asynchronous clear active: high
-- Clock enable active: high
--
------------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity generator_reg6 is
port (
CLR : in std_logic;
CE : in std_logic;
CLK : in std_logic;
DATA : in std_logic_vector (5 downto 0);
Q : out std_logic_vector (5 downto 0)
);
end entity;



architecture reg_arch6 of generator_reg6 is
signal TEMP_Q_0: std_logic_vector (5 downto 0);
begin

process (CLK, CLR)
begin

if CLR = '1' then
TEMP_Q_0 <= (others => '0');
elsif rising_edge(CLK) then
if CE = '1' then
TEMP_Q_0 <= DATA;
end if;
end if;

end process;

Q <= TEMP_Q_0;

end architecture;


------------------------------------------------------------------------------------
-- DESCRIPTION : Flip-flop D type
-- Width: 8
-- Clock active: high
-- Asynchronous clear active: high
-- Clock enable active: high
--
------------------------------------------------------------------------------------



library IEEE;
use IEEE.std_logic_1164.all;

entity generator_reg8 is
port (
CLR : in std_logic;
CE : in std_logic;
CLK : in std_logic;
DATA : in std_logic_vector (7 downto 0);
Q : out std_logic_vector (7 downto 0)
);
end entity;



architecture reg_arch8 of generator_reg8 is
signal TEMP_Q_1: std_logic_vector (7 downto 0);
begin

process (CLK, CLR)
begin

if CLR = '1' then
TEMP_Q_1 <= (others => '0');
elsif rising_edge(CLK) then
if CE = '1' then
TEMP_Q_1 <= DATA;
end if;
end if;

end process;

Q <= TEMP_Q_1;

end architecture;


------------------------------------------------------------------------------------
-- DESCRIPTION : Name : Analog Generator
--
------------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity generator is
port (
DATA : in std_logic_vector(5 downto 0);
PR : in std_logic;
FR : in std_logic;
CLR : in std_logic;
CE : in std_logic;
Q : out std_logic_vector(7 downto 0);
CLK : in std_logic);

end generator;



architecture generator_arch of generator is

component generator_acc6
port(
A : in STD_LOGIC_VECTOR(5 downto 0);
CE : in STD_LOGIC;
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(5 downto 0));
end component;

component generator_adder
port (
A : in STD_LOGIC_VECTOR(5 downto 0);
B : in STD_LOGIC_VECTOR(5 downto 0);
Q : out STD_LOGIC_VECTOR(5 downto 0));
end component;

component generator_and2
port (
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
O : out STD_LOGIC
);
end component;

component generator_sin
port (
OE : in STD_LOGIC;
ADDRESS : in STD_LOGIC_VECTOR(5 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0) );
end component;

component generator_reg6
port (
CE : in STD_LOGIC;
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR(5 downto 0);
Q : out STD_LOGIC_VECTOR(5 downto 0));
end component;

component generator_reg8
port (
CE : in STD_LOGIC;
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR(7 downto 0);
Q : out STD_LOGIC_VECTOR(7 downto 0));
end component;

signal CE_U1 : STD_LOGIC;
signal CE_U2 : STD_LOGIC;
signal cur_FR : STD_LOGIC_VECTOR (5 downto 0);
signal cur_PR : STD_LOGIC_VECTOR (5 downto 0);
signal def_FR : STD_LOGIC_VECTOR (5 downto 0);
signal VAL : STD_LOGIC_VECTOR (7 downto 0);
signal VAL1 : STD_LOGIC_VECTOR (7 downto 0);
signal VAL2 : STD_LOGIC_VECTOR (7 downto 0);
signal VAL3 : STD_LOGIC_VECTOR (7 downto 0);
signal VAL4 : STD_LOGIC_VECTOR (7 downto 0);
signal PRFR : STD_LOGIC_VECTOR (5 downto 0);

begin

U1 : generator_reg6
port map(
CE => CE_U1,
CLK => CLK,
CLR => CLR,
DATA => DATA,
Q => cur_PR);

U6 : generator_sin
port map(
OE => '1',
ADDRESS => PRFR,
Q => VAL4);


VAL <= VAL4;
U2 : generator_reg6
port map(
CE => CE_U2,
CLK => CLK,
CLR => CLR,
DATA => DATA,
Q => def_FR);

U3 : generator_adder
port map(
A => cur_PR,
B => cur_FR,
Q => PRFR);

U4 : generator_acc6
port map(
A => def_FR,
CE => CE,
CLR => CLR,
CLK => CLK,
Q => cur_FR);

U7 : generator_reg8
port map(
CE => CE,
CLR => CLR,
CLK => CLK,
DATA => VAL,
Q => Q);

U8 : generator_and2
port map(
I0 => CE,
I1 => FR,
O => CE_U2);

U9 : generator_and2
port map(
I0 => CE,
I1 => PR,
O => CE_U1);

end architecture generator_arch;
加法器源程序 相应加法器的测试向量（test bench)

// download from: www.pld.com.cn & www.fpga.com.cn 


module test_counter;

reg clk, rst;
wire [7:0] count;

counter #(5,10) dut (count,clk,rst);

initial // Clock generator
  begin
    clk = 0;
    #10 forever #10 clk = !clk;
  end
  
initial	// Test stimulus
  begin
    rst = 0;
    #5 rst = 1;
    #4 rst = 0;
    #50000 $stop;
  end
  
initial
    $monitor($stime,, rst,, clk,,, count); 
    
endmodule