BBS: Bulletin board system. A computer program which may be accessed by remote users through a modem, allowing them to post questions, view responses, and download files.
benchmarking: A type of program execution that allows you to track the number of CPU cycles consumed by a specific section of code.
BI bit: See break interrupt (BI) bit.
BIG bit: A field that specifies how the input/output (I/O) port wait-state register is mapped. This bit is stored in the wait-state control register (CWSR).
At reset, BIG = 0.
big-endian: An addressing protocol in which bytes are numbered from left to right within a word. More significant bytes in a word have lower numbered addresses. Endian ordering is specific to hardware and is determined at reset. See also little endian.
binding: Associating or linking together two complementary software objects.
pin: A general-purpose input pin that can be tested by conditional BIO instructions that cause a branch when an external device drives BIO low.
bitBLT: Bit-aligned block transfer. Transfer of a block of pixels from one location in a bitmap to another.
bit detection: The special logic that supports leftmost-one, rightmost-one,leftmost-bit-change, and rightmost-bit-change detection.
bitmap: 1) A digital representation of an image in which bits are mapped to pixels. 2) A block of memory used to hold raster images in a device-specific format.
bit plane: A bit storage array (plane) used to store a particular bit of each pixel of an image. The 0 bit of each pixel is stored in bit plane 0, the first bit of each pixel is stored in bit plane 1, and so on. (TMS320C8x)
bit-reversed addressing: Addressing in which bits of an address are reversed in order to speed the processing of algorithms, such as Fourier transform algorithms.
bit-reversed indexed addressing: A method of indirect addressing that allows efficient I/O operations by resequencing the data points in a radix-2 fast Fourier transform (FFT) program. The direction of carry propagation in the auxiliary register arithmetic unit (ARAU) is reversed.
bits per pixel (BPP): The number of bits used to represent the color value
of each pixel in a digitized image.
BK: See block-size register.
BKR: See BSP receive buffer size register.
BKX: See BSP transmit buffer size register.
blanking: The process of extinguishing the scanning beam during horizontal and vertical retrace periods. See also active time; blanking area.
blanking area: The area of a display that is not active but rather blanked.
No pixels are displayed in the blanking area. Vertical and horizontal retrace occur during blanking. See also blanking pulse.
blanking pulse: A positive or negative pulse developed during retrace, appearing at the end of each field; used to blank out scanning lines during the vertical or horizontal retrace interval. See also blanking.
blocked: The state of a task that is not ready to execute. A task can be blocked either by being suspended or by voluntarily choosing to wait for an event such as the arrival of a message or signal.
block miss: A cache miss in which the addressed block is not resident in the cache. The least recently used (LRU) algorithm determines which existing cache block is discarded. If the cache contains any modified data (master processor (MP) data cache only), then any modified subblocks are written back to external memory before the requested subblock is brought into cache.
block move address register (BMAR): A memory-mapped register that holds an address value for use with block moves or multiply/accumu-lates. (TMS320C5x)
block repeat active flag (BRAF) bit: A field that indicates a block repeat is currently active. This bit is normally set when the repeat block (RPTB)
instruction is executed and is cleared when the block repeat counter register (BRCR) decrements below 0. Writing a 0 to this bit deactivates block repeat. At reset, BRAF = 0. This bit is stored in the processor mode status register for the TMS320C5x. (TMS320C5x)
block repeat counter register (BRC, BRCR): A register that specifies the number of times a block of code is to be repeated when a block repeat is performed.
block repeat program address end register (PAER, REA): A memorymapped register that contains the end address of the segment of code being repeated.
block repeat program address start register (PASR, RSA): A memorymapped register that contains the start address of the segment of code being repeated.
block-size register (BK): A register used for defining the length of a program block to be repeated in repeat mode.
block write: A nonstandard packet transfer that allows the transfer controller (TC) to perform multicolumn write operations.
BMAR: See block move address register.
BOB: See byte ordering bit.
boot: The process of loading a program into program memory.
boot loader: An on-chip program that loads and executes programs received from a host processor through standard memory devices (including EPROM), with and without handshake, or through the serial port to RAM at power up.
pin: The pin that enables the on-chip boot loader. When BOOT is held BOOT low, the processor executes the boot loader program after a hardware is held high, the processor skips execution of the boot reset. When BOOT loader and accesses off-chip program-memory at reset. (TMS320C2xx,TMS320C24x)
boundary scan: The use of scan registers on the border of a chip or section of logic to capture the pin states. By scanning these registers, all pin states can be transmitted through the JTAG port for analysis.
BPP: See bits per pixel.
BR: See bus request (BR) pin.
BRAF: See block repeat active flag (BRAF) bit.
branch: A switching of program control to a nonsequential programmemory address.
BRC: See block repeat counter register.
BRCR: See block repeat counter register.
BRD: See baud-rate divisor register.
BRE: See autobuffering receiver enable (BRE) bit.
break interrupt (BI) bit: A bit within the I/O status register (IOSR) that indicates when a break is detected on the asynchronous receive (RX) pin.(TMS320C2xx)
breakpoint: A place in a routine specified by an instruction, instruction digit,
or other condition, where the routine may be interrupted by external intervention or by a monitor routine.
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