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EDA第4次

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2015-01-06 23:03:34    评分
 

3-3 试分别用IF_THEN语句、WHEN_ELSECASE语句的表达方式写出4选一多路选择器的VHDL程序,选通控制端有4个输入:S0,S1,S2,S3。当且仅当S0=0时:Y=A;S1=0时:Y=B;S2=0Y=C;S3=0Y=D

1.IF_THEN语句:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

      PORT(

        A,B,C,D,S0,S1,S2,S3 :  IN  STD_LOGIC;

                       Y:  OUT  STD_LOGIC

);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

SIGNAL  S :  STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

S<=S3 & S2 & S1 & S0;

PROCESS(S3,S2,S1,S0)  BEGIN

     IF (S=1110) THEN Y<=A;

ELSIF (S=1101”) THEN Y<=B;

ELSIF (S=1011”) THEN Y<=C;

ELSIF (S=0111”) THEN Y<=D;

END IF;

END PROCESS;

END ARCHITECTURE BHV;

2.WHEN_ELSE语句:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

      PORT(

        A,B,C,D,S0,S1,S2,S3 :  IN  STD_LOGIC;

                       Y:  OUT  STD_LOGIC

);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

SIGNAL  S  :  STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

      S<= S<=S3 & S2 & S1 & S0;

      Y<=A WHEN  S=1110 ELSE;

      B WHEN  S=1101”  ELSE;

  C WHEN  S=1011”  ELSE

D WHEN S=0111”  ELSE

;

END ARCHITECTURE BHV;

3.CASE语句

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

      PORT(

        A,B,C,D,S0,S1,S2,S3 :  IN  STD_LOGIC;

                       Y:  OUT  STD_LOGIC

);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

SIGNAL  S :  STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

S<=S3 & S2 & S1 & S0;

PROCESS(S3,S2,S1,S0)  BEGIN

CASE (S) IS

 WHEN1110 =>Y<=A;

WHEN1101 =>Y<=B;

WHEN1011 =>Y<=C;

WHEN0111 =>Y<=D;

WHEN  OTHERS => NULL;

END CASE;

END PROCESS;

END ARCHITECTURE BHV;

4WITH SELECT语句:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX41A IS

      PORT(

        A,B,C,D,S0,S1,S2,S3 :  IN  STD_LOGIC;

                       Y:  OUT  STD_LOGIC

);

END ENTITY MUX41A;

ARCHITECTURE BHV OF MUX41A IS

SIGNAL  S :  STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

S<=S3 & S2 & S1 & S0;

WITH S SELECT

Y<=A  WHEN 1110

Y<=B  WHEN 1101”;

Y<=C  WHEN 1011”;

Y<=D  WHEN 0111”;

UNAFFECTED WHEN OTHERS;

END ARCHITECTURE BHV;

3-4 给出全减器的VHDL描述。要求:

(1)          首先设计半减器,然后用例化语句将它们连接起来,h_suber是半减器,diff是输出差,s_out是借位输出,

Sub_in是借位输入。

(2)          根据图设计全减器。以全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项目。(减法运算是 x-y-sub_in=diffr

答:半减器:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY h_suber IS

PORT (

          x, y:  IN  STD_LOGIC;

     diff , s_out:  OUT  STD_LOGIC

        );

END ENTITY h_suber;

ARCHITECTURE one OF h_suber IS

   BEGIN

     Diff   <=  x XOR y;

s_out  <=(NOT x ) AND y;

END ARCHITECTURE one;

二输入或门;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY or2a IS

PORT (

          a, b:  IN  STD_LOGIC;

            c:  OUT  STD_LOGIC

        );

END ENTITY or2a;

ARCHITECTURE one1 OF or2a IS

   BEGIN

   c  <=  a OR b;

END ARCHITECTURE one1;

全加器:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY f_suber IS

  PORT (

x,y, Sub_in: IN  STD_LOGIC;

      diffr , sub_out: OUT  STD_LOGIC

);

END ENTITY f_suber;

ARCHITECTURE fd2 OF f_suber IS

   COMPONENT h_suber

PORT (

         x, y:  IN  STD_LOGIC;

     diff , s_out:  OUT  STD_LOGIC

          );

COMPONENT or2a

PORT (

         a, b:  IN  STD_LOGIC;

           c:  OUT  STD_LOGIC

          );

END COMPONENT;

SIGNAL net1, net2 ,net3 :  STD_LOGIC;

BEGIN

U1 : h_suber PORT MAP(x=>x,y=>y, s_out=>net2, diff=>net1);

U2: h_suber PORT MAP(net1, Sub_in, net3, diffr);

U3:  or2a PORT MAP( a=>net2,b=>net3,c=> sub_out);

END ARCHITECTURE fd2;

      8位减法器:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTUTY suber8B IS

PORT (

         A, B:  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);

       Sub_in:  IN  STD_LOGIC;

        COUT: OUT  STD_LOGIC;

DOUT: OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);

);

END ENTUTY suber8B;

ARCHITECTURE  BHV OF suber8B IS

SIGNAL DATA :  STD_LOGIC_VECTOR(8 DOWNTO 0);

    BEGIBN

DATA <=(‘0’ & A)+ (‘0’ & B)+ (‘00000000’ & Sub_in);

COUT <=DATA (8);

DOUT <=DATA (7 DOWNTO 0);

END ARCHITECTURE  BHV




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