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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY d3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0);

DOUT: OUT BIT_VECTOR(7 DOWNTO 0));

END d3to8;

ARCHITECTURE behave OF d3to8 IS

BEGIN

PROCESS (DIN)

BEGIN

CASE CONV_INTEGER(DIN) IS

WHEN 0 => DOUT<="00000001";

WHEN 1 => DOUT<="00000010";

WHEN 2 => DOUT<="00000100";

WHEN 3 => DOUT<="00001000";

WHEN 4 => DOUT<="00010000";

WHEN 5 => DOUT<="00100000";

WHEN 6 => DOUT<="01000000";

WHEN 7 => DOUT<="10000000";

WHEN OTHERS => NULL;

END CASE;