代码:
驱动代码:
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity fengmq is
port (clk: in std_logic;
fmq: out std_logic
);
end fengmq;
architecture behave of fengmq is
--signal count: std_logic;
begin
process (clk)
begin
if clk'event and clk='1' then
-- count<=clk;
end if;
end process ;
fmq<=clk;
end behave ;
分频代码:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fp2k is
port(clk_48MHZ: in std_logic;
clk_2KHZ: out std_logic
);
end fp2k;
architecture behav of fp2k is
signal clk_2KHZ_r: std_logic;
signal count : std_logic_vector(14 downto 0);
begin
process (clk_48MHZ)
begin
if clk_48MHZ'event and clk_48MHZ='1' then
if count="110000110100111"then
count<=(others=>'0');
clk_2KHZ_r<=not clk_2KHZ_r;
else count<=count+1;
clk_2KHZ<=clk_2KHZ_r;
end if;
end if;
end process;
end behav;
电路图:
数字时钟代码:
总图:
主程序:实现分秒时功能,对于分秒时可以分三个模块编写,这里把这三个模块放在一起:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Counter_m_f_s is
port
(
clk,reset : in std_logic ;
bcd_h_m : out std_logic_vector(3 downto 0); --秒钟个位输出
bcd_l_m : out std_logic_vector(3 downto 0); --秒钟十位输出
bcd_l_f : out std_logic_vector(3 downto 0); --分钟个位输出
bcd_h_f : out std_logic_vector(3 downto 0); --分钟十位输出
bcd_l_s : out std_logic_vector(3 downto 0); --时钟个位输出
bcd_h_s : out std_logic_vector(3 downto 0); --时钟十位输出
up : out std_logic
);
end Counter_m_f_s ;
architecture behav of Counter_m_f_s is
signal bcd_h_m_r : std_logic_vector(3 downto 0); --秒钟个位内部信号
signal bcd_l_m_r : std_logic_vector(3 downto 0); --秒钟十位内部信号
signal bcd_h_f_r : std_logic_vector(3 downto 0); --分钟个位内部信号
signal bcd_l_f_r : std_logic_vector(3 downto 0); --分钟十位内部信号
signal bcd_h_s_r : std_logic_vector(3 downto 0); --时钟个位内部信号
signal bcd_l_s_r : std_logic_vector(3 downto 0); --时钟个位内部信号
signal up_r1 : std_logic;
signal up_r2 : std_logic;
begin
U1: process (clk, reset) --秒钟
begin
--if reset='0' then
-- bcd_h_m_r <="0000"; bcd_l_m_r <="0000"; up_r1 <='0';
--else
if clk'event and clk='1' then
if bcd_h_m_r ="0101" and bcd_l_m_r ="1001" then
bcd_h_m_r <="0000"; --59秒,分钟进一
bcd_l_m_r <="0000";
up_r1 <= '1' ;
else
if bcd_l_m_r(3 downto 0) = "1001" then --秒的个位为9,十位进一,分钟不进为
bcd_l_m_r(3 downto 0)<= "0000" ;
bcd_h_m_r(3 downto 0) <= bcd_h_m_r(3 downto 0) + 1 ;
up_r1 <= '0';
else
bcd_l_m_r(3 downto 0) <= bcd_l_m_r(3 downto 0) + 1 ;
up_r1 <= '0';
end if;
end if;
end if;
--end if;
end process;
bcd_h_m <= bcd_h_m_r;
bcd_l_m <= bcd_l_m_r;
U2: process (up_r1 , reset) --分钟
begin
if reset='0' then
bcd_h_f_r <="0000"; bcd_l_f_r <="0000"; up_r2 <='0';
else
if up_r1'event and up_r1='1' then
if bcd_h_f_r ="0101" and bcd_l_f_r ="1001" then --59分,时钟进一
bcd_h_f_r <="0000";
bcd_l_f_r <="0000";
up_r2 <= '1' ;
else
if bcd_l_f_r(3 downto 0) = "1001" then --分的个位为9,十位进一,时钟不进位
bcd_l_f_r(3 downto 0) <= "0000" ;
bcd_h_f_r(3 downto 0) <= bcd_h_f_r(3 downto 0) + 1 ;
up_r2 <= '0';
else
bcd_l_f_r(3 downto 0) <= bcd_l_f_r(3 downto 0) + 1 ;
up_r2 <= '0';
end if;
end if;
end if;
end if;
end process;
bcd_h_f <= bcd_h_f_r;
bcd_l_f <= bcd_l_f_r;
U3: process ( up_r2 , reset) -- 时钟
begin
if reset='0' then
bcd_h_s_r <="0000"; bcd_l_s_r <="0000"; up <='0';
else
if up_r2'event and up_r2='1' then
if bcd_h_s_r ="0010" and bcd_l_s_r ="0011" then --23时,时钟进一。
bcd_h_s_r <="0000";
bcd_l_s_r <="0000";
up <= '1' ;
else
if bcd_l_s_r(3 downto 0) = "1001" then
bcd_l_s_r(3 downto 0)<= "0000" ;
bcd_h_s_r(3 downto 0) <= bcd_h_s_r(3 downto 0) + 1 ;
up <= '0';
else
bcd_l_s_r(3 downto 0) <= bcd_l_s_r(3 downto 0) + 1 ;
up <= '0';
end if;
end if;
end if;
end if;
end process;
bcd_h_s <= bcd_h_s_r;
bcd_l_s <= bcd_l_s_r;
end architecture behav;
数码管动态驱动 :
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_Arith.ALL;
USE IEEE.STD_LOGIC_Unsigned.ALL;
ENTITY xianshi_led IS
PORT(
clk_1k: IN STD_LOGIC;
d: IN STD_LOGIC_VECTOR(31 DOWNTO 0); --输入要显示的数据
dig: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --数码管选择输出引脚
seg: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --数码管段输出引脚
);
END ENTITY;
ARCHITECTURE one OF xianshi_led IS
SIGNAL seg_r: STD_LOGIC_VECTOR(7 DOWNTO 0); --定义数码管输出寄存器
SIGNAL dig_r: STD_LOGIC_VECTOR(7 DOWNTO 0); --定义数码管选择输出寄存器
SIGNAL disp_dat: STD_LOGIC_VECTOR(3 DOWNTO 0); --定义显示数据寄存器
SIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0); --定义计数寄存器
BEGIN
dig<=dig_r;
seg<=seg_r;
PROCESS(clk_1k)
BEGIN
IF RISING_EDGE(clk_1k) THEN
count<=count+1;
END IF;
END PROCESS;
PROCESS(clk_1k)
BEGIN
IF RISING_EDGE(clk_1k) THEN
CASE count IS
WHEN "000"=> disp_dat<=d(31 DOWNTO 28); --第一个数码管
WHEN "001"=> disp_dat<=d(27 DOWNTO 24); --第二个数码管
WHEN "010"=> disp_dat<=d(23 DOWNTO 20); --第三个数码管
WHEN "011"=> disp_dat<=d(19 DOWNTO 16); --第四个数码管
WHEN "100"=> disp_dat<=d(15 DOWNTO 12); --第五个数码管
WHEN "101"=> disp_dat<=d(11 DOWNTO 8); --第六个数码管
WHEN "110"=> disp_dat<=d(7 DOWNTO 4); --第七个数码管
WHEN "111"=> disp_dat<=d(3 DOWNTO 0); --第八个数码管
END CASE;
CASE count IS --选择数码管显示位
WHEN "000"=> dig_r<="01111111"; --选择第一个数码管显示
WHEN "001"=> dig_r<="10111111"; --选择第二个数码管显示
WHEN "010"=> dig_r<="11011111"; --选择第三个数码管显示
WHEN "011"=> dig_r<="11101111"; --选择第四个数码管显示
WHEN "100"=> dig_r<="11110111"; --选择第五个数码管显示
WHEN "101"=> dig_r<="11111011"; --选择第六个数码管显示
WHEN "110"=> dig_r<="11111101"; --选择第七个数码管显示
WHEN "111"=> dig_r<="11111110"; --选择第八个数码管显示
END CASE;
END IF;
END PROCESS;
PROCESS(disp_dat)
BEGIN
CASE disp_dat IS
WHEN X"0"=> seg_r<=X"c0";--显示0
WHEN X"1"=> seg_r<=X"f9";--显示1
WHEN X"2"=> seg_r<=X"a4";--显示2
WHEN X"3"=> seg_r<=X"b0";--显示3
WHEN X"4"=> seg_r<=X"99";--显示4
WHEN X"5"=> seg_r<=X"92";--显示5
WHEN X"6"=> seg_r<=X"82";--显示6
WHEN X"7"=> seg_r<=X"f8";--显示7
WHEN X"8"=> seg_r<=X"80";--显示8
WHEN X"9"=> seg_r<=X"90";--显示9
WHEN X"a"=> seg_r<=X"88";--显示a
WHEN X"b"=> seg_r<=X"83";--显示b
WHEN X"c"=> seg_r<=X"c6";--显示c
WHEN X"d"=> seg_r<=X"a1";--显示d
WHEN X"e"=> seg_r<=X"86";--显示e
WHEN X"f"=> seg_r<=X"8e";--显示f
END CASE;
END PROCESS;
END;
另外再加1hz分频和2KHZ分频。
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