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verilog程序：
module vga
#(
//------------水平扫描常量--------------
 parameter LinePeriod = 12'd1040,
 parameter H_SyncPulse = 10'd120,
 parameter H_BackPorch = 10'd61,
 parameter H_ActivePix = 10'd806,
//------------垂直扫描常量-------------- 
 parameter FramePeriod = 12'd666,
 parameter V_SyncPulse = 10'd6,
 parameter V_BackPorch = 10'd21,
 parameter V_ActivePix = 10'd604
)

(
 input clk,
 input rst,
 output H_Sync,
 output V_Sync,
 output [2:0] VGA_R,
 output [2:0] VGA_G,
 output [1:0] VGA_B
);

//-----------------水平扫描计数-----------------
 reg[11:0] X_cnt;
 always @(posedge clk or negedge rst) begin
  if(!rst)
   X_cnt <= 12'b1;
  else if(X_cnt == LinePeriod) X_cnt <= 12'b1;
  else X_cnt <= X_cnt + 1'b1;
 end
 
//-------------水平扫描信号HSYNC计产生-------------
 reg H_Sync_r;
 always @(posedge clk or negedge rst) begin
  if(!rst) H_Sync_r <= 1'b1;
  else if(X_cnt == 12'b1) H_Sync_r <= 1'b0;
  else if(X_cnt >= H_SyncPulse) H_Sync_r <= 1'b1;
 end
 assign H_Sync = H_Sync_r;
 
//-----------------垂直扫描计数-----------------
 reg[11:0] Y_cnt;
 always @(posedge clk or negedge rst) begin
  if(!rst) Y_cnt <= 12'b1;
  else if(Y_cnt == FramePeriod) Y_cnt <= 12'b1;
  else if(X_cnt == LinePeriod) Y_cnt <= Y_cnt + 1'b1;  //水平扫描完后垂直
 end
//-------------垂直扫描信号VSYNC计产生-------------
 reg V_Sync_r;
 always @(posedge clk or negedge rst) begin
  if(!rst) V_Sync_r <= 1'b1;
  else if(Y_cnt == 12'b1) V_Sync_r <= 1'b0;
  else if(Y_cnt >= V_SyncPulse) V_Sync_r <= 1'b1;
 end
 assign V_Sync = V_Sync_r;
 
//----------------有效显示区标志-------------------
 wire valid;
 assign valid = (X_cnt>=(H_SyncPulse+H_BackPorch))&&(X_cnt<(H_SyncPulse+H_BackPorch+H_ActivePix))&&
      (Y_cnt>=(V_SyncPulse+V_BackPorch))&&(Y_cnt<(V_SyncPulse+V_BackPorch+V_ActivePix));

 wire[9:0] x_dis;
 wire[9:0] y_dis;
 assign x_dis = X_cnt - (H_SyncPulse + H_BackPorch );
 assign y_dis = Y_cnt - (V_SyncPulse + V_BackPorch );
 
/**************VGA色彩信号产生***************
 RGB = 000   黑色 RGB = 100 红色
  = 001   蓝色  = 101 紫色
  = 010 绿色  = 110 黄色
  = 011 青色  = 111 白色
*******************************************/ 
 
 reg[15:0] rom_addr;  //ROM地址
 wire[7:0] rom_data;  //ROM数据
 rom PIC_rom
 (
  .address(rom_addr),
  .clock(clk),
  .q(rom_data)
 );
 
 reg [7:0] vga_RGB;
 always @(posedge clk or negedge rst) begin
  if(!rst) 
   begin
   vga_RGB <= 8'b0;
   rom_addr <= 16'b0;
   end
  else if(valid)
   begin
   if((x_dis >= 10'd336 && x_dis < 10'd464) && (y_dis >= 10'd250 && y_dis < 10'd350))
    begin
    vga_RGB <= rom_data;
    rom_addr <= rom_addr + 1'b1;
    if(rom_addr == 12799) rom_addr <= 16'b0;    
    end
   else vga_RGB <= 8'b000_001_11;
   end
  else vga_RGB <= 8'b0;
 end

 assign VGA_R = vga_RGB[7:5];
 assign VGA_G = vga_RGB[4:2];
 assign VGA_B = vga_RGB[1:0];

endmodule

才做到AD现在，下个文件测试看有没错的