这些小活动你都参加了吗?快来围观一下吧!>>
电子产品世界 » 论坛首页 » 嵌入式开发 » FPGA » 用 ise怎么仿真 vhdl

共2条 1/1 1 跳转至

用 ise怎么仿真 vhdl

菜鸟
2014-04-12 09:39:10     打赏

这个是键盘的程序 是对的   用ise综合对了   想知道  这个文件现在已经是顶层文件了吗   我想在板子上实现下一步该做什么了  


----------------------------------------------------------------------------------

-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:53:46 04/09/2014 
-- Design Name: 
-- Module Name:    keyboard - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;


entity keyboard is
port(
k_data:in std_logic;
k_clock:in std_logic;
out_data:out std_logic_vector(5 downto 0));
end keyboard;


architecture Behavioral of keyboard is
  signal tempdata:std_logic_vector(11 downto 0):="000000000000";
signal count,count1:integer range 0 to 11:=0;
signal datascan,previous_data:std_logic_vector(7 downto 0);
signal out_data_temp:std_logic_vector(5 downto 0);
signal chang_clk:std_logic:='0';


begin
out_data<=out_data_temp;
process(k_clock)
begin
if(k_clock'event and k_clock='0')then
     if (count=10)then
  count<=0;
datascan<=tempdata(8 downto 1);
else
count<=count+1;
tempdata(count)<=k_data;
end if;
    end if;


if(k_clock'event and k_clock='1')then
if(count=10)then
count1<=0;
previous_data<=datascan;
chang_clk<='1';
else
count1<=count1+1;
chang_clk<='0';
end if;
end if;
end process;
process(chang_clk)
begin
   if(chang_clk'event and chang_clk='1')then
      if((not(datascan=previous_data))and((datascan="11110000")or(previous_data="11110000")))then
 out_data_temp<="000000";
       else
  case datascan is
when"00010101"=>out_data_temp<="000001";
when"00011101"=>out_data_temp<="000010";
when"00100100"=>out_data_temp<="000011";
when"00101101"=>out_data_temp<="000100";
when"00101100"=>out_data_temp<="000101";
when"00110101"=>out_data_temp<="000110";
when"00111100"=>out_data_temp<="000111";
when"00010110"=>out_data_temp<="010001";
when"00011110"=>out_data_temp<="010010";
when"00100110"=>out_data_temp<="010011";
when"00100101"=>out_data_temp<="010100";
when"00101110"=>out_data_temp<="010101";
when"00110110"=>out_data_temp<="010110";
when"00111101"=>out_data_temp<="010111";
when"00011100"=>out_data_temp<="100001";
when"00011011"=>out_data_temp<="100010";
when"00100011"=>out_data_temp<="100011";
when"00101011"=>out_data_temp<="100100";-
when"00110100"=>out_data_temp<="100101";
when"00110011"=>out_data_temp<="100110";
when"00111011"=>out_data_temp<="100111";
when others=>out_data_temp<=out_data_temp;
end case;
end if;
end if;
end process;

end ;




工程师
2014-04-12 14:53:52     打赏
2楼
稍等,正在联系版主,周末见谅。。。

共2条 1/1 1 跳转至

回复

匿名不能发帖!请先 [ 登陆 注册 ]