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习题3-5
用VHDL设计3-8译码器
(1)when_else语句：
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY decoder3to8_1 IS 
PORT (  DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 
         DOUT : OUT BIT_VECTOR (7 DOWNTO 0)); 
END decoder3to8_1; 
ARCHITECTURE BHV OF decoder3to8_1 IS 
BEGIN 	
    DOUT <= “00000001” WHEN DIN="000" ELSE 
    DOUT <= “00000010” WHEN DIN="001" ELSE 
    DOUT <= “00000100” WHEN DIN="010" ELSE 
    DOUT <= “00001000” WHEN DIN="011" ELSE 
    DOUT <= “00010000” WHEN DIN="100" ELSE 
    DOUT <= “00100000” WHEN DIN="101" ELSE 
    DOUT <= “01000000” WHEN DIN="110" ELSE 
    DOUT <= “10000000” WHEN DIN="111" ELSE 
           NULL;
END BHV; 
(2)case语句：
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY decoder3to8_2 IS
PORT( A : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 
      Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); 
END decoder3to8_2 ; 
ARCHITECTURE BHV OF decoder3to8_2 IS
BEGIN 
  PROCESS(A) 
  BEGIN 
     CASE  A  IS 
		WHEN "000" => Y <= "00000001"; 
		WHEN "001" => Y <="00000010";  
		WHEN "010" => Y <="00000100"; 
		WHEN "011" => Y <="00001000"; 
		WHEN "100" => Y <="00010000"; 
		WHEN "101" => Y <="00100000"; 
		WHEN "110" => Y <="01000000";
		WHEN "111" => Y <="10000000"; 
		WHEN OTHERS => Y <="00000000"; 
     END CASE; 
  END PROCESS;
END BHV;
(3)if_else语句
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY decoder3to8_3 IS 
PORT (  S : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 
        Y : OUT BIT_VECTOR (7 DOWNTO 0)); 
END decoder3to8_3; 
ARCHITECTURE BHV OF decoder3to8_3 IS 
BEGIN 
S <= S2 & S1 & S0;
  PROCESS(S) 
  BEGIN 
            IF (S="000") THEN Y <= "00000001"; 
         ELSIF (S="001") THEN Y <="00000010";  
         ELSIF (S="010") THEN Y <="00000100";  
         ELSIF (S="011") THEN Y <="00001000";  
         ELSIF (S="100") THEN Y <="00010000";  
         ELSIF (S="101") THEN Y <="00100000";  
         ELSIF (S="110") THEN Y <="01000000";  
         ELSIF (S="111") THEN Y <="10000000"; 
         ELSE NULL; 
         END IF ; 
  END PROCESS;
END BHV;
(4)移位操作符
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY decoder3to8_4 IS 
PORT (  DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0); 
       DOUT : OUT BIT_VECTOR (7 DOWNTO 0)); 
END decoder3to8_4; 
ARCHITECTURE BHV OF decoder3to8_4 IS 
BEGIN 
    DOUT <=”00000001” SLL CONV INTEGER(DIN);
END BHV;

第四种方法最节省逻辑资源。



习题3-14
用循环语句设计一个7人投票表决器
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY vote_7 IS
PORT ( DIN : IN STD_LOGIC_VECTOR (6 DOWNTO 0) ;
         Y : OUT STD_LOGIC;
      CNTH : OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
END vote_7;
ARCHITETURE BHV OF vote_7 IS 
BEGIN
PROCESS(DIN)
VARIABLE Q : STD_LOGIC_VECTOR(2 DOWNTO 0);
   BEGIN 
    Q :=”000”;
    FOR n IN 0 TO 6 LOOP
      IF (DIN(n)=’1’) THEN Q:=Q+1;
      END IF;
    END LOOP;
    CNTH <= Q;
IF Q>=4 THEN Y<=’1’;
ELSE Y<=’0’;
END IF;
END PROCESS;
END BHV;