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hellok
工程师
2012-11-28 23:48:51     打赏
11楼

//*********************************************************
//文件名称：  key.v
//说明：      手把手教你学习FPGA—按键篇 实验一 按键控制LED亮灭
//           按KEY1，数码管在0-9变化
//版本号：    V0.0  2012.11.26
//*********************************************************

module key(sys_clk, rst_n, key, led_seg, led_bit);

input sys_clk, rst_n;
input [7:0] key;
output [7:0] led_seg;
output [7:0] led_bit;

//reg [7:0] led;
reg [3:0] count10;
reg [7:0] led_seg;
wire [7:0] led_bit;
wire key_scan;
reg key_samp;
reg key_samp_r;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp <= 1'b1;
  else
      key_samp <= key[0];
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp_r <= 1'b1;
  else
      key_samp_r <= key_samp;
end

assign key_scan = key_samp_r & (~key_samp);

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      count10 <= 4'd0;//led <= 8'b1111_1111;
  else if (key_scan)
      begin
    count10 <= count10 + 1;//led <= ~led;
    if (count10 == 4'd9)
        count10 <= 4'd0;
    end
//  else
//      led <= led;
end

always @ (count10)
begin
    case(count10)
     4'd0 : led_seg = 8'hc0;
    4'd1 : led_seg = 8'hf9;
    4'd2 : led_seg = 8'ha4;
    4'd3 : led_seg = 8'hb0;
    4'd4 : led_seg = 8'h99;
    4'd5 : led_seg = 8'h92;
    4'd6 : led_seg = 8'h82;
    4'd7 : led_seg = 8'hf8;
    4'd8 : led_seg = 8'h80;
    4'd9 : led_seg = 8'h90;
    default: led_seg = 8'h86;
  endcase
end

assign led_bit = 8'b1111_1110;

endmodule


//*********************************************************
//文件名称：  key.v
//说明：      手把手教你学习FPGA—按键篇 实验二 按键消抖控制LED亮灭
//           按KEY1，数码管在0-9变化
//版本号：    V0.0  2012.11.28
//*********************************************************
module key(sys_clk, rst_n, key, led_seg, led_bit);

input sys_clk, rst_n;
input [7:0] key;
//output [7:0] led;
output [7:0] led_seg;
output [7:0] led_bit;

//reg [7:0] led;
reg [19:0] delay_cnt;
wire key_scan;
wire key_low;
reg key_samp;
reg key_samp_r;
reg key_rst;
reg key_rst_r;
reg [3:0] count10;
reg [7:0] led_seg;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp <= 1'b1;
  else
      key_samp <= key[0];
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_samp_r <= 1'b1;
  else
      key_samp_r <= key_samp;
end

assign key_scan = key_samp_r & (~key_samp);

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 20'h0;
  else if (key_scan)
      delay_cnt <= 20'h0;
  else
      delay_cnt <= delay_cnt + 1'b1;
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_rst <= 1'b1;
  else if (delay_cnt == 20'hfffff)
      key_rst <= key[0];
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      key_rst_r <= 1'b1;
  else
      key_rst_r <= key_rst;
end

assign key_low = key_rst_r & (~key_rst);

/*always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      led <= 8'b1111_1111;
  else if (key_low)
      led <= ~led;
  else
      led <= led;
end*/

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      count10 <= 4'd0;
  else if (key_low)
      begin
    count10 <= count10 + 1;
    if (count10 == 4'd9)
        count10 <= 4'd0;
    end
end

always @ (count10)
begin
    case(count10)
     4'd0 : led_seg = 8'hc0;
    4'd1 : led_seg = 8'hf9;
    4'd2 : led_seg = 8'ha4;
    4'd3 : led_seg = 8'hb0;
    4'd4 : led_seg = 8'h99;
    4'd5 : led_seg = 8'h92;
    4'd6 : led_seg = 8'h82;
    4'd7 : led_seg = 8'hf8;
    4'd8 : led_seg = 8'h80;
    4'd9 : led_seg = 8'h90;
    default: led_seg = 8'h86;
  endcase
end

assign led_bit = 8'b1111_1110;

endmodule



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hellok
工程师
2012-11-29 22:27:08     打赏
12楼

//*********************************************************
//文件名称：  buzz.v
//说明：      手把手教你学习FPGA—蜂鸣器篇 实验一 蜂鸣器发出救护车鸣笛声
//           蜂鸣器发出报警声
//版本号：    V0.0  2012.11.29
//*********************************************************

module buzz(sys_clk, rst_n, beep);

input sys_clk, rst_n;
output beep;

reg beep;
reg [23:0] div_cnt;
reg [14:0] delay_cnt;
wire [14:0] delay_end;

parameter clk_divider0 = 113635;
parameter clk_divider1 = 56817;
assign delay_end = div_cnt[23] ? clk_divider0 : clk_divider1;

always @ (posedge sys_clk or negedge rst_n)   //一种音调时长
begin
    if (!rst_n)
      div_cnt <= 24'd0;
  else
      div_cnt <= div_cnt + 1'b1;
end

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= delay_end;
  else if (delay_cnt == 15'd0)
      begin
    beep <= ~beep;
    delay_cnt <= delay_end;
    end
  else
      delay_cnt <= delay_cnt - 1'b1;
end

endmodule
//*********************************************************
//文件名称：  music.v
//说明：      手把手教你学习FPGA—蜂鸣器篇 实验二 硬件电子琴
//           自动播放梁祝
//版本号：    V0.0  2012.11.29
//*********************************************************

module music(sys_clk, beep);
  
input sys_clk;
output beep; 

reg   beep_r; 
reg [7:0] state;
reg [15:0] count, count_end;
reg [23:0] count1;

parameter   L_3 = 16'd75850,        
            L_5 = 16'd63776,       
            L_6 = 16'd56818,
   L_7 = 16'd50618,
   M_1 = 16'd47774, 
   M_2 = 16'd42568, 
   M_3 = 16'd37919, 
   M_5 = 16'd31888, 
   M_6 = 16'd28409,
   H_1 = 16'd23912;  
parameter TIME = 12000000;
         
assign beep = beep_r;

always@(posedge sys_clk)
begin
 count <= count + 1'b1;
 if(count == count_end)
 begin
  count <= 16'h0;
  beep_r <= !beep_r;
 end
end

always @ (posedge sys_clk)
begin
 if(count1 < TIME)
  count1 = count1 + 1'b1;
 else
 begin
  count1 = 24'd0;
  if(state == 8'd66)
   state = 8'd0;
  else
   state = state + 1'b1;
  case(state)
   8'd0,8'd1,8'd2,8'd3:     count_end = L_3;
   8'd4,8'd5,8'd6:                     count_end = L_5;
   8'd7:                       count_end = L_6;
   8'd8,8'd9,8'd10:            count_end = M_1;
   8'd11:         count_end = M_2;
   8'd12:               count_end = L_6;
   8'd13:               count_end = M_1; 
   8'd14,8'd15:                   count_end = L_5;
   8'd16:               count_end = M_1;
   8'd17,8'd18:       count_end = L_5;
   8'd19,8'd20,8'd21:              count_end = M_5;
   8'd22:                           count_end = H_1;
   8'd23:                        count_end = M_6;
   8'd24:                  count_end = M_5;
   8'd25:               count_end = M_3;
   8'd26:                        count_end = M_5;
   8'd27,8'd28,8'd29,8'd30,8'd31,
   8'd32,8'd33,8'd34,8'd35,8'd36,8'd37:count_end = M_2;
   8'd38:               count_end = M_3;
   8'd39,8'd40:      count_end = L_7;
   8'd41,8'd42:                count_end = L_6;
   8'd43,8'd44,8'd45:      count_end = L_5;
   8'd46:               count_end = L_6;
   8'd47,8'd48:               count_end = M_1;
   8'd49,8'd50:                count_end = M_2;
   8'd51,8'd52:       count_end = L_3;
   8'd53,8'd54,8'd55:            count_end = M_1;
   8'd56,8'd57:          count_end = L_5;
   8'd58:               count_end = M_1;
   8'd59,8'd60,8'd61,8'd62,8'd63,
   8'd64,8'd65,8'd66:               count_end = L_5;
  endcase
 end
end

endmodule

/*module music (sys_clk, rst_n, key, beep);

input sys_clk ,rst_n;
input [7:0] key;
output beep;

reg beep;
reg [15:0] delay_cnt;
reg [15:0] delay_end;

always @ (posedge sys_clk or negedge rst_n)
begin
    if (!rst_n)
      delay_cnt <= 16'd0;
  else if ((delay_cnt == delay_end) & (!(delay_end == 16'hffff)))
      begin
    delay_cnt <= 16'd0;
    beep <= ~beep;
    end
  else
      delay_cnt <= delay_cnt + 1'b1;
end

always @ (key)
begin
    case (key)
      8'b1111_1110 : delay_end = 16'd47774;
    8'b1111_1101 : delay_end = 16'd42568;
    8'b1111_1011 : delay_end = 16'd37919;
    8'b1111_0111 : delay_end = 16'd35791;
    8'b1110_1111 : delay_end = 16'd31888;
    8'b1101_1111 : delay_end = 16'd28409;
    8'b1011_1111 : delay_end = 16'd25309;
    8'b0111_1110 : delay_end = 16'd23912;
    8'b0111_1101 : delay_end = 16'd21282;
    8'b0111_1011 : delay_end = 16'd18961;
    8'b0111_0111 : delay_end = 16'd17897;
    8'b0110_1111 : delay_end = 16'd15944;
    8'b0101_1111 : delay_end = 16'd14205;
    8'b0011_1111 : delay_end = 16'd12655;
    default : delay_end = 16'd65535;
  endcase
end

endmodule
*/


评论
w013016
助工
2012-11-30 11:20:08     打赏
13楼
学习！！！

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freebsdsean
助工
2013-09-23 12:54:27     打赏
14楼
assign delay_end=div_cnt[24]? clk_divider0:clk_divider1;此句在Q11web版本中编译时报错代码10219，如何排除？

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共14条 2/2 ‹ 1 2 跳转至页

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