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module scan_led(clk,rst,sm_seg,sm_bit);
input clk,rst;
output[7:0] sm_seg;
output[7:0] sm_bit;
reg[7:0] sm_seg;
reg[7:0] sm_bit;

reg[15:0] cnt_scan;
reg[4:0] dataout_buf;

always@(posedge clk or negedge  rst)
begin
 if(!rst) begin
  cnt_scan<=0;
  
  end
 else begin
  cnt_scan<=cnt_scan+1'b1;
  end
end

always @(cnt_scan)
begin
   case(cnt_scan[15:13])
       3'b000 :
          sm_bit = 8'b1111_1110;
       3'b001 :
          sm_bit = 8'b1111_1101;
       3'b010 :
          sm_bit = 8'b1111_1011;
       3'b011 :
          sm_bit = 8'b1111_0111;
       3'b100 :
         sm_bit = 8'b1110_1111;
       3'b101 :
         sm_bit = 8'b1101_1111;
       3'b110 :
          sm_bit = 8'b1011_1111;
       3'b111 :
         sm_bit = 8'b0111_1111;
       default :
          sm_bit = 8'b1111_1110;
    endcase
end

always@(sm_bit)
begin
 case(sm_bit)
  8'b1111_1110:
   dataout_buf=0;
  8'b1111_1101:
   dataout_buf=1;
  8'b1111_1011:
   dataout_buf=2;
  8'b1111_0111:
   dataout_buf=3; 
  8'b1110_1111:
   dataout_buf=4;
  8'b1101_1111:
   dataout_buf=5;
  8'b1011_1111:
   dataout_buf=6;
  8'b0111_1111:
   dataout_buf=7;
  default:
   dataout_buf=8;
  endcase
end

always@(dataout_buf)
begin
 case(dataout_buf)
      4'h0 : sm_seg = 8'b00000011;   // "0"
   4'h1 : sm_seg = 8'b10011111;   // "1"
   4'h2 : sm_seg = 8'b00100101;   // "2"
   4'h3 : sm_seg = 8'b00001101;   // "3"
   4'h4 : sm_seg = 8'b10011001;   // "4"
   4'h5 : sm_seg = 8'b01001001;   // "5"
   4'h6 : sm_seg = 8'b01000001;   // "6"
   4'h7 : sm_seg = 8'b00011111;   // "7"
  /* 4'h8 : sm_seg = 8'h80;   // "8"
   4'h9 : sm_seg = 8'h90;   // "9"
   4'ha : sm_seg = 8'h88;   // "a"
   4'hb : sm_seg = 8'h83;   // "b"
   4'hc : sm_seg = 8'hc6;   // "c"
   4'hd : sm_seg = 8'ha1;   // "d"
   4'he : sm_seg = 8'h86;   // "e"
   4'hf : sm_seg = 8'h8e;   // "f"*/
  endcase
end

endmodule 


上图

来个vhdl lcd1602的   注释乱码咯 见谅啊~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lcd is   
port(clk:in std_logic;                      
     lcd_rs,lcd_rw,lcd_e:out std_logic;
     dataout:out std_logic_vector(7 downto 0));
end lcd;

architecture behave of lcd is
signal p:std_logic_vector(15 downto 0);
signal m:std_logic_vector(7 downto 0);
signal t,n:std_logic:='0';
begin
process(clk,n)
begin
if(n='0')then
 if(clk'event and clk='1')then           ---¸ßµçƽ´¥·¢·½Ê½
  p<=p+1;
  if(p>"0111111111111111")then        --   5000000000m/3760
   t<='1';
  else
   t<='0';
  end if;
 end if;
end if;
end process;

lcd_e<=t;                         --//ÿ¸öÂö³å¿ª¹ØʹÄÜ

process(t,m)
begin
if(t'event and t='1')then
 m<=m+1;
 if(m>39)then
  n<='1';
 end if;
 if(m<6 or m=23)then           --//µ±m<5ʱΪ³õʼ»¯m=6£¬m=23ʱΪÉ趨ÐÐ Æ䶼ΪдָÁî
  lcd_rs<='0';
  lcd_rw<='0';
 else                          --//ÆäÓà¾ùΪдÊý¾Ý
  lcd_rs<='1';
  lcd_rw<='0';  
 end if;
end if;

case m is
 when"00000001"=>dataout<=X"38";   --//lcd1602 ³õʼ»¯º¯ÊýÖ¸Áî 0x38 0x0c 0x06 0x80 0x01
 when"00000010"=>dataout<=X"0C";
 when"00000011"=>dataout<=X"06";
 when"00000100"=>dataout<=X"80";
 when"00000101"=>dataout<=X"01";
 
 when"00000110"=>dataout<=X"40";   ------www.eepw.com  --
 when"00000111"=>dataout<=X"77";      
 when"00001000"=>dataout<=X"77";
 when"00001001"=>dataout<=X"77";
 when"00001010"=>dataout<=X"2E";
 when"00001011"=>dataout<=X"65";
 when"00001100"=>dataout<=X"65";
 when"00001101"=>dataout<=X"70";
 when"00001110"=>dataout<=X"77";
 when"00001111"=>dataout<=X"2E";
 when"00010000"=>dataout<=X"63";
 when"00010001"=>dataout<=X"6F";
 when"00010010"=>dataout<=X"6D";     
 when"00010100"=>dataout<=X"20";
 when"00010101"=>dataout<=X"20";
 when"00010110"=>dataout<=X"20";
 when"00010111"=>dataout<=X"20";
 
 when"00011000"=>dataout<=X"C0";    --//»»ÐР  aihai0002275
 
 when"00011001"=>dataout<=X"20";
 when"00011010"=>dataout<=X"20";
 when"00011011"=>dataout<=X"20";
 when"00011100"=>dataout<=X"20";
 when"00011101"=>dataout<=X"61";
 when"00011110"=>dataout<=X"69";
 when"00011111"=>dataout<=X"68";
 when"00100000"=>dataout<=X"61";
 when"00100001"=>dataout<=X"69";
 when"00100010"=>dataout<=X"30";  
 when"00100011"=>dataout<=X"30";
 when"00100100"=>dataout<=X"30";      
 when"00100101"=>dataout<=X"32";      
 when"00100110"=>dataout<=X"32";      
 when"00100111"=>dataout<=X"37";       
  when"00101000"=>dataout<=X"35";      
 when others=>dataout<=X"20";      --//¿Õ¸ñ   
end case;
end process;

end behave;

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