* ---------------------------------------------------------------
clk(0,1,2)输入的时钟信号
gate(0,1,2)输入的门控信号
out（0,1,2）输出信号
data 数据总线
rd 输入读信号
wr 输入写操作
a0,a1 端口选择信号
cs 片选信号
control（0,1,2）控制字
控制口编程状态机：
state=00-----未编程或完毕
01-----已写控制字（等待输入数据）
10-----已写1字节数据（等待输入下一数据）
启动计数标志:
start(0,1,2)_Y=0, 不启动
1, 启动（当编程完毕）
装入数值开始计数标志
count(0,1,2)_Y=0-----未启动（未装入计数初值寄存器内容）或结束
1-----已装入，作减1计数
count (0,1,2) 输出的计数器数值
count(0,1,2)_b 输入的新的计数的初值
count(0,1,2)_b1 输入的计数的初值
g（0,1,2）_Y 门控信号的计数标志
b（0，1,2） 读操作时控制高低位
function 计数方式函数，BCD码计数和二进制计数
------------------------------------------------------------------------ */
module timer(//input
clk0,clk1,clk2,data,gate0,gate1,gate2,a0,a1,wr,rd,cs,out0,out1,out2,
//output
count0,count1,count2,count0_Y,count1_Y,count2_Y,control0,control1,control2,
start0_Y,start1_Y,start2_Y,count0_b,count1_b,count2_b,state);
input clk0,clk1,clk2,gate0,gate1,gate2,a0,a1,wr,rd,cs;
inout [7:0] data;
output out0,out1,out2,start0_Y,start1_Y,start2_Y,count0_Y,count1_Y,count2_Y;
output [15:0] count0,count1,count2,count0_b,count1_b,count2_b;
output [1:0] state;
output [7:0] control0,control1,control2;
reg [7:0] control0,control1,control2;
reg [15:0] count0_b,count1_b,count2_b,count0_b1,count1_b1,count2_b1,count0,count1,count2,count_rd;
reg [1:0] state;
reg start0_Y,start1_Y,start2_Y,out0,out1,out2,count0_Y,count1_Y,count2_Y,g0,g1,g2,g0_Y,g1_Y,g2_Y;
wire clock0,clock1,clock2,b0,b1,b2;
function [15:0] countnew;
input [15:0] cnt;
reg [3:0] temp1,temp2,temp3,temp4;
begin
{temp4,temp3,temp2,temp1} = cnt;
temp1 = temp1-1;
if(temp1 == 4'b1111) begin
temp1 = 4'b1001;
temp2 = temp2-1;
if(temp2 == 4'b1111) begin
temp2 = 4'b1001;
temp3 = temp3-1;
if(temp3 == 4'b1111) begin
temp3 = 4'b1001;
temp4 = temp4-1;
if(temp4 == 4'b1111) begin
temp3 = 4'b1001;
end
end
end
end
countnew = {temp4,temp3,temp2,temp1};
end
endfunction
always@(negedge rd)
begin
if(!a0 && !a1)count_rd<=count0;
else if(a0 && !a1)count_rd<=count1;
else if(!a0 && a1)count_rd<=count2;
end
always @(posedge wr)
if(cs==0)
begin
case(state)
2'b00:
if (cs==0 && a0==1 && a1==1 && data[7:6]==2'b00)
begin control0<=data;start0_Y<=0;state<=2'b01; end
else if (cs==0 && a0==1 && a1==1 && data[7:6]==2'b01)
begin control1<=data;start1_Y<=0;state<=2'b01; end
else if (cs==0 && a0==1 && a1==1 && data[7:6]==2'b10)
begin control2<=data;start2_Y<=0;state<=2'b01; end
2'b01:
if(control0[5:4]==2'b11 && a0==0 && a1==0)
begin state<=2'b10;count0_b[7:0]<=data; end
else if(control0[5:4]==2'b01 && a0==0 && a1==0)
begin state<=2'b01;start0_Y<=1;count0_b[7:0]<=data;count0_b[15:8]<=0;
end
else if(control0[5:4]==2'b10 && a0==0 && a1==0)
begin state<=2'b01;start0_Y<=1;count0_b[7:0]<=0;count0_b[15:8]<=data;
end
else if(control1[5:4]==2'b11 && a0==1 && a1==0)
begin state<=2'b10;count1_b[7:0]<=data; end
else if(control1[5:4]==2'b01 && a0==1 && a1==0)
begin state<=2'b01;start1_Y<=1;count1_b[7:0]<=data;count1_b[15:8]<=0;
end
else if(control1[5:4]==2'b10 && a0==1 && a1==0)
begin state<=2'b01;start1_Y<=1;count1_b[7:0]<=0;count1_b[15:8]<=data;
end
else if(control2[5:4]==2'b11 && a0==0 && a1==1)
begin state<=2'b10;count2_b[7:0]<=data; end
else if(control2[5:4]==2'b01 && a0==0 && a1==1)
begin state<=2'b01;start2_Y<=1;count2_b[7:0]<=data;count2_b[15:8]<=0;
end
else if(control2[5:4]==2'b10 && a0==0 && a1==1)
begin state<=2'b01;start2_Y<=1;count2_b[7:0]<=0;count2_b[15:8]<=data;
end
else state<=2'b00;
2'b10:
if(control0[5:4]==2'b11 && a0==0 && a1==0)
begin state<=2'b01;start0_Y<=1;count0_b[15:8]<=data; end
else if(control1[5:4]==2'b11 && a0==1 && a1==0)
begin state<=2'b01;start1_Y<=1;count1_b[15:8]<=data; end
else if(control2[5:4]==2'b11 && a0==0 && a1==1)
begin state<=2'b01;start2_Y<=1;count2_b[15:8]<=data; end
else state<=2'b00;
endcase
end
//端口0
assign b0=(!rd && !cs && !a0 && !a1 && clock0)?1'b1:1'b0;
assign data=(!rd && !cs && !a0 && !a1 && clock0 && b0)?count_rd[7:0]:8'bzzzzzzzz;
assign data=(!rd && !cs && !a0 && !a1 && !clock0 && !b0)?count_rd[15:8]:8'bzzzzzzzz;
assign clock0=!clk0 && start0_Y;
always@(posedge gate0 )
if(gate0)g0<=1;
else g0<=0;
always@(negedge start0_Y or negedge clock0)
if(start0_Y==0)
begin count0_b1<=0;
count0_Y<=0;
if(control0[3:1]==3'b000)out0<=0;
else out0<=1;
end
else
begin
case(control0[3:0])
4'b0000:
if(gate0 && start0_Y==1)
begin
if(count0_b1!=count0_b)
count0_b1<=count0_b;count0<=count0_b;out0<=0;count0_Y<=1;
end
else
if(count0==0)
begin count0<=0;out0<=1;count0_Y<=0; end
else if (count0==1)
begin count0<=count0-1;out0<=1;
end
else begin count0<=count0-1;out0<=0; end
4'b0001:
if(gate0 && start0_Y==1)
if(count0_b1!=count0_b)
begin
count0_b1<=count0_b;count0<=count0_b;out0<=0;count0_Y<=1;
end
else
if(count0==0)
begin count0<=0;out0<=1;count0_Y<=0; end
else if (count0==1)
begin count0<=countnew(count0);out0<=1;
end
else begin count0<=countnew(count0);out0<=0; end
4'b0010:
if(start0_Y==1)
begin
if(g0)
g0_Y<=1;
if(g0_Y==1)
begin
count0<=count0_b;
out0<=0;
g0_Y<=0;
count0_Y<=1;
end
else if(count0==0)
begin
count0<=0;
out0<=1;
count0_Y<=0;
end
else if(count0==1)
begin
count0<=count0-1;
out0<=1;
end
else begin count0<=count0-1;out0<=0; end
end
4'b0011:
if(start0_Y==1)
begin
if(g0)
g0_Y<=1;
if(g0_Y==1)
begin
count0<=count0_b;
out0<=0;
g0_Y<=0;
count0_Y<=1;
end
else if(count0==0)
begin
count0<=0;
out0<=1;
count0_Y<=0;
end
else if(count0==1)
begin
count0<=countnew(count0);
out0<=1;
end
else begin count0<=countnew(count0);out0<=0; end
end
4'b1010:
if(start0_Y==1)
begin
if(g0)
g0_Y<=1;
if(g0_Y==1)
begin
count0<=count0_b;
out0<=1;
g0_Y<=0;
count0_Y<=1;
end
else if(count0==0)
begin
count0<=0;
out0<=1;
count0_Y<=0;
end
else if(count0==1)
begin
out0<=0;
count0<=count0-1;
end
else begin count0<=count0-1;out0<=1; end
end
4'b1011:
if(start0_Y==1)
begin
if(g0)
g0_Y<=1;
if(g0_Y==1)
begin
count0<=count0_b;
out0<=1;
g0_Y<=0;
count0_Y<=1;
end
else if(count0==0)
begin
count0<=0;
out0<=1;
count0_Y<=0;
end
else if(count0==1)
begin
out0<=0;
count0<=countnew(count0);
end
else begin count0<=countnew(count0);out0<=1; end
end
default: count0_Y<=0;
endcase
end
关键词：
Verilog 8253
STM32
MCU
通讯及无线技术
物联网技术
电子DIY
板卡试用
基础知识
软件与操作系统
我爱生活
小e食堂