让我也来试试
module ADC_Select( input CLK, input Reset_n, output reg F_S_CLK_0, output reg F_S_CLK_SELF ); //if F_S_CLK_0 = 1, ALL ADC has the same CLK from PLL_0; //if F_S_CLk_SELF =1,ADC's CLKs are from different PLL, //forexample PLL1,PLL2,PLL3,PLL4,PLL5,PLL6,PLL7,PLL8 always @ (posedge CLK or negedge Reset_n) if(!Reset_n)begin F_S_CLK_0 <= 1'b1; F_S_CLK_SELF <= 1'b0; end else begin F_S_CLK_0 <= 1'b1; F_S_CLK_SELF <= 1'b0; end endmodule
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