这些小活动你都参加了吗?快来围观一下吧!>>
电子产品世界 » 论坛首页 » 嵌入式开发 » FPGA » 小弟刚刚学习VHDL语言大家能帮忙看看这段代码哪里错了吗

共3条 1/1 1 跳转至

小弟刚刚学习VHDL语言大家能帮忙看看这段代码哪里错了吗

菜鸟
2017-05-19 11:35:24     打赏
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PSGtraffic is
port(clk:in std_logic;
     people:in std_logic;
 cnttime: out std_logic_vector(7 downto 0);
 carled: out std_logic_vector(3 downto 0);
 peopleled: out std_logic(3 downto 0));
 end PSGtraffic;
ARCHITECTURE behave OF PSGtraffic IS
type statetype is (CGPR,CYPR,CRPG);
 SIGNAL STATE: statetype := CGPR;
 SIGNAL cnt :std_logic_vector(7 downto 0);
begin
 process(clk,people,cnt)
 begin 
   if (clk'event and clk='1')then
      if clk/=0 then
        if cnt(3 downto 0)=x"0"then
           cnt(7 downto 4)<=cnt(7 downto 4)-1;
        cnt(3 downto 0)<=x"9";
 else
           cnt(3 downto 0)<=cnt(3 downto 0)-1;
     end if;
   end if;
  case state is
     when CGPR =>
       carled<="0010";
       peopleled<="0100";
       if people ="1"and cnt=0 then
          state <= CYPR;
          cnt <=x"3"AFTER 30s;
       end if;
     when CYPR =>
       carled<="0001";
       peopleled<="0100";
          if cnt = 0 then 
 state <= CRPG;
          cnt <=x"15";
       end if;
     when CRPG =>
       carled<="0100";
       peopleled<="0010";
       if cnt = 0 then
         if people ="0" and cnt=0 then
         state <= CGPR;
         cnt <=x"30";
      end if;
           when others => NULL;
end case;
       end if;
       cnttime<=cnt;
 end process;
end behave;
 
 



管理员
2017-05-19 14:05:01     打赏
2楼
哈哈  好复杂的样子  期待大神来解答

专家
2017-05-22 08:39:19     打赏
3楼
这个真不懂,帮楼主加人气。

共3条 1/1 1 跳转至

回复

匿名不能发帖!请先 [ 登陆 注册 ]