EEPW论坛

rt，分频是在quartus仿真时，仿真结果不清楚，不知道在实际中会怎么样？
module divid(clk_out,clk_in,rst_n );
output   clk_out;
input   clk_in,rst_n;
reg   clk_out;
reg[10:0]   count;   //  count from 0 to N/2
parameter  N = 2400;
always @(posedge clk_in)
begin
    if(!rst_n)
    begin
        count <= 0;   clk_out <= 0;
    end
    else if(count == N/2-1)
    begin
        count <= 0;   clk_out <= ~clk_out;
    end
    else
        count <= count + 1;
end
endmodule