EEPW论坛

上传FPGA DIY的tcl脚本文件，利用它可以自动分配引脚。
http://share.eepw.com.cn/share/download/id/79306

还能自动分配引脚。
这个高级啊~~

前段时间很忙，耽误了一段时间，现在上传数码管的显示程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_Unsigned.ALL;
ENTITY showseg7 IS
  PORT(clk_p: IN STD_LOGIC;
       dig:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--数码管选择输出引脚
       seg:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--数码管段输出引脚
END ENTITY showseg7;
ARCHITECTURE one OF showseg7 IS
 SIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0);--定义数码管输出寄存器
 SIGNAL seg_r: STD_LOGIC_VECTOR(7 DOWNTO 0);--定义数码管选择输出寄存器
 SIGNAL dig_r: STD_LOGIC_VECTOR(7 DOWNTO 0);--定义显示数据寄存器
 SIGNAL disp_r:STD_LOGIC_VECTOR(2 DOWNTO 0);--定义计数寄存器
BEGIN
  PROCESS(clk_p)                              
   BEGIN
    IF RISING_EDGE(clk_p) THEN
  IF count="111" THEN count<="000";
   ELSE count<=count+1;
  END IF;
    END IF;
  END PROCESS;

  PROCESS(count)
   BEGIN
    CASE count IS
      WHEN "000" => disp_r<="000";dig_r<="01111111";seg_r<="11000000";--显示0
      WHEN "001" => disp_r<="001";dig_r<="10111111";seg_r<="11111001";--显示1
      WHEN "010" => disp_r<="010";dig_r<="11011111";seg_r<="10100100";--显示2
      WHEN "011" => disp_r<="011";dig_r<="11101111";seg_r<="10110000";--显示3
      WHEN "100" => disp_r<="100";dig_r<="11110111";seg_r<="10011001";--显示4
      WHEN "101" => disp_r<="101";dig_r<="11111011";seg_r<="10010010";--显示5
      WHEN "110" => disp_r<="110";dig_r<="11111101";seg_r<="10000010";--显示6
      WHEN "111" => disp_r<="111";dig_r<="11111110";seg_r<="11111000";--显示7
      WHEN OTHERS => NULL;
    END CASE;
END PROCESS;
  seg<=seg_r;
  dig<=dig_r;
END ARCHITECTURE one;

数码管显示图片

数字钟程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY yimaqi IS
PORT(clk2:IN STD_LOGIC;
     doe:IN STD_LOGIC_VECTOR(23 DOWNTO 0);
     dig2:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
     seg2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ;
ARCHITECTURE example OF yimaqi IS
SIGNAL a:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
SIGNAL b:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk2)
BEGIN
IF clk2'event and clk2='1' THEN
  IF a="101" THEN a<="000";ELSE a<=a+1;
  END IF;
END IF;
END PROCESS;
PROCESS(a)
BEGIN
CASE a IS
WHEN"101"=>b<=doe(3 DOWNTO 0);dig2<="111110";
WHEN"100"=>b<=doe(7 DOWNTO 4);dig2<="111101";
WHEN"011"=>b<=doe(11 DOWNTO 8);dig2<="111011";
WHEN"010"=>b<=doe(15 DOWNTO 12);dig2<="110111";
WHEN"001"=>b<=doe(19 DOWNTO 16);dig2<="101111";
WHEN"000"=>b<=doe(23 DOWNTO 20);dig2<="011111";
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
PROCESS(b)
BEGIN
CASE b IS
WHEN"0000"=>seg2<="11000000";
WHEN"0001"=>seg2<="11111001";
WHEN"0010"=>seg2<="10100100";
WHEN"0011"=>seg2<="10110000";
WHEN"0100"=>seg2<="10011001";
WHEN"0101"=>seg2<="10010010";
WHEN"0110"=>seg2<="10000010";
WHEN"0111"=>seg2<="11111000";
WHEN"1000"=>seg2<="10000000";
WHEN"1001"=>seg2<="10010000";
WHEN OTHERS=>seg2<="11111111";
END CASE;
END PROCESS;
END example;

数字钟视频：

蜂鸣器程序：利用键盘控制音调
library ieee;
use ieee.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity fengmq is
port (clk: in std_logic;
      fmq: out std_logic

);
end fengmq;
 
architecture  behave of fengmq is
--signal count: std_logic;
begin
process (clk)
begin
if clk'event and clk='1' then
  -- count<=clk;
   end if;
 end process ;
 fmq<=clk;
 end behave ;

蜂鸣器视频：

1602显示字符代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LCD1602 is
port ( clk :in std_logic;
      lcd_rs:out std_logic;
      lcd_rw:out std_logic;
      lcd_e: out std_logic;
      data:out std_logic_vector(7 downto 0)
);
end LCD1602;
architecture one of LCD1602 is
signal bcd: std_logic_vector(5 downto 0);
--signal cnt: std_logic_vector(9 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then
   bcd<=bcd+1;
 --  cnt<=cnt+1;
   case bcd is
   when "000000"=>
         lcd_rs<='0';
         lcd_e<='1';
         data<="00111000";
   when "000001"=>
         lcd_rs<='0';
         lcd_e<='0';
        
   when "000010"=>
         lcd_rs<='0';
         lcd_e<='1';
         data<="00001100";
   when "000011"=>
         lcd_rs<='0';
         lcd_e<='0';
   when "000101"=>
         lcd_rs<='0';
         lcd_e<='0';      
   when "000110"=>      --xian E
         lcd_rs<='1';
         lcd_e<='1';
         data<="01000101";
   when "000111"=>
         lcd_rs<='1';
         lcd_e<='0'; 
     
   when "001000"=>
         lcd_rs<='0';
         lcd_e<='1';
         data<="10000010";
   when "001001"=>
         lcd_rs<='0';
         lcd_e<='0';     
   when "001010"=>        --xian  E
         lcd_rs<='1';
         lcd_e<='1';
         data<="01000101"; 
   when "001011"=>
         lcd_rs<='1';
         lcd_e<='0';   
    
   when "001100"=>          
         lcd_rs<='0';
         lcd_e<='1';
         data<="10000011";
   when "001101"=>
         lcd_rs<='0';
         lcd_e<='0';     
   when "001110"=>       --xian P
         lcd_rs<='1';
         lcd_e<='1';
         data<="01010000"; 
   when "001111"=>
         lcd_rs<='1';
         lcd_e<='0';
   
   when "010000"=>          
         lcd_rs<='0';
         lcd_e<='1';
         data<="10000100";
   when "010001"=>
         lcd_rs<='0';
         lcd_e<='0';    
   when "010010"=>       --xian w
         lcd_rs<='1';
         lcd_e<='1';
         data<="01010111"; 
   when "010011"=>
         lcd_rs<='1';
         lcd_e<='0';  
         lcd_e<='0';                                                                  
   when others=>null;           
   end case;
   end if;
end process;  
end ;