EEPW论坛

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity TEST is
port(
CLK:in STD_LOGIC;
DataBus: inout STD_LOGIC_VECTOR(7 downto 0);
WR: in STD_LOGIC;
RD: in STD_LOGIC
);
end TEST;
architecture TEST_arch of TEST is
process (CLK)
variable State:integer range 1 downto 0;
variable Data:STD_LOGIC_VECTOR(7 downto 0);
begin
IF CLK'EVENT AND CLK ='1' THEN
case State is
when 0 =>
DataBus <= "ZZZZZZZZ";
if WR = '0' AND RD = '1' then --WRITE
Data := DataBus ;
State := 1;
elsif WR = '1' AND RD = '0' then --READ
DataBus <= Data;
State := 1;
end if;
when 1 =>
if WR = '1' AND RD = '1' then
State := 0;
end if;
END IF;
end process;
end TEST_arch;

太简洁了。
这两个程序在响应的硬件上都可以实现的。
XILINX确实是不错。