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LED作业
从内向两边流水
module led_run(sys_clk,
               sys_rstn,
               led1,led2
                  );
input            sys_clk;
input            sys_rstn;
output  [3:0]    led1    ;
output  [3:0]    led2    ;
reg     [3:0]    led1    ;

reg     [3:0]    led2    ;
reg     [24:0]   delay_cnt;
always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       delay_cnt<=25'd0;
   else
                   begin
           if(delay_cnt==25'd24999999)
           delay_cnt<=25'd0;
       else
           delay_cnt<=delay_cnt+1'b1;
     end
  end 
always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       led1<=8'b0111;
   else
           begin
           if(delay_cnt==25'd24999999)
      led1<={led1[3:0],led1[3]};
    else
                                     led1<=led1;
     end
  end 
always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       led2<=4'b1110;
   else
           begin
           if(delay_cnt==25'd24999999)
      led2<={led2[0],led2[3:1]};
    else
                                     led2<=led2;
     end
  end 

endmodule 

按键偏1作业

稍后传视频

代码：
module key1_9(sys_clk,
           sys_rstn,
     key_in,
     led_out
     );
input      sys_clk;
input      sys_rstn;
input      key_in;
output   [7:0]  led_out;
reg      [7:0] led_out;
reg     [24:0]   delay_cnt1;
reg     [11:0]   delay_cnt;
reg     [1:0]   delay_cnt2;
always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       delay_cnt1<=25'd0;
   else
                   begin
           if(delay_cnt1==25'd39999999)
           delay_cnt1<=25'd0;
       else
           delay_cnt1<=delay_cnt1+1'b1;
     end
  end 
always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       delay_cnt2<=1'd0;
   else if(delay_cnt1==25'd39999999)
          delay_cnt2<=1 ;
      else delay_cnt2<=0;
      end
always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       delay_cnt<=25'd0;
      else if(delay_cnt2==0)
     delay_cnt<=delay_cnt;
     else
               begin
           if(delay_cnt==10)
           delay_cnt<=25'd0;
       else
       if(!key_in)
           delay_cnt<=delay_cnt+1'b1;
       
     end
  end 
always@(posedge sys_clk or negedge sys_rstn)
       begin
            if(!sys_rstn)
              led_out<=8'b00000000;
      else if(delay_cnt==0)
               led_out<=8'b00000001;
    else
               if(delay_cnt==1)
               led_out<=8'b01001111;
       else
               if(delay_cnt==2)
               led_out<=8'b00010010;
       else
               if(delay_cnt==3)
               led_out<=8'b00000110;
       else
               if(delay_cnt==4)
               led_out<=8'b01001100;
       else
               if(delay_cnt==5)
               led_out<=8'b00100100;
       else
               if(delay_cnt==6)
               led_out<=8'b00100000;
       else
               if(delay_cnt==7)
               led_out<=8'b00001111;
       else
               if(delay_cnt==8)
               led_out<=8'b00000000;
       else
               if(delay_cnt==9)
               led_out<=8'b00000100;
      
   end
endmodule
   

最近工作有点忙，好长时间没更新帖子了。

消抖按键控制1到9显示

代码：
module key_doudong(sys_clk,
                   sys_rstn,
       key_in,
       led_out
       );
input              sys_clk;
input              sys_rstn;
input              key_in;
output             led_out;

reg      [7:0]     led_out;
reg      [19:0]    delay_cnt;
reg      [4:0]     delay_cnt_s;
wire               key_scan;
wire               key_low;
reg                key_samp;
reg                key_samp_r;
reg                key_rst;
reg                key_rst_r;
always@(posedge sys_clk or negedge sys_rstn)
    begin
      if(!sys_rstn)
       key_samp<=1'b1;
  else
      key_samp<=key_in;
  end
always@(posedge sys_clk or negedge sys_rstn)
 begin
      if(!sys_rstn)
       key_samp_r<=1'b1;
  else
      key_samp_r<=key_in;
  end
assign key_scan=key_samp_r&(~key_samp);
always@(posedge sys_clk or negedge sys_rstn)
       begin
     if(!sys_rstn)
      delay_cnt<=20'h0;
   else if(key_scan)
       delay_cnt<=20'h0;
   else
       delay_cnt<=delay_cnt+1'b1;
     end

always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
      key_rst<=1'b1;
   else if(delay_cnt==20'hfffff)
      key_rst<=key_in;
  end
always@(posedge sys_clk or negedge sys_rstn)
     begin
       if(!sys_rstn)
      key_rst_r<=1'b1;
   else
   key_rst_r<=key_rst;
 end
assign key_low=key_rst_r&(~key_rst);

always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
       delay_cnt_s<=4'd0;
     
     else if(delay_cnt_s==10)
           delay_cnt_s<=4'd0;
    else
       if(key_low)
           delay_cnt_s<=delay_cnt_s+1'b1;
       
    
  end 
always@(posedge sys_clk or negedge sys_rstn)
       begin
            if(!sys_rstn)
              led_out<=8'b00000000;
      else if(delay_cnt_s==0)
               led_out<=8'b00000001;
    else
               if(delay_cnt_s==1)
               led_out<=8'b01001111;
       else
               if(delay_cnt_s==2)
               led_out<=8'b00010010;
       else
               if(delay_cnt_s==3)
               led_out<=8'b00000110;
       else
               if(delay_cnt_s==4)
               led_out<=8'b01001100;
       else
               if(delay_cnt_s==5)
               led_out<=8'b00100100;
       else
               if(delay_cnt_s==6)
               led_out<=8'b00100000;
       else
               if(delay_cnt_s==7)
               led_out<=8'b00001111;
       else
               if(delay_cnt_s==8)
               led_out<=8'b00000000;
       else
               if(delay_cnt_s==9)
               led_out<=8'b00000100;
      
   end

endmodule

拨码开关控制八进制数码显示


代码：
module led_display_sw1_8 (sys_clk,
                          sys_rstn,
          key_in,
              sm_seg,
              sm_bit
              );
input               sys_clk;
input               sys_rstn;
output     [7:0]    sm_seg;
output     [7:0]    sm_bit;
reg        [7:0]    sm_seg;
reg        [7:0]    sm_bit;
reg        [3:0]    disp_dat;
input      [7:0]    key_in;
always@(key_in)
    begin
    case(key_in)
      8'b11111111:disp_dat = 4'h0;
      8'b11111110:disp_dat = 4'h1;
    8'b11111101:disp_dat = 4'h2;
    8'b11111011:disp_dat = 4'h3;
    8'b11110111:disp_dat = 4'h4;
    8'b11101111:disp_dat = 4'h5;
    8'b11011111:disp_dat = 4'h6;   
    8'b10111111:disp_dat = 4'h7;
    8'b01111111:disp_dat = 4'h8;
    endcase
   end

 always@(disp_dat)
     begin
       case (disp_dat)
         4'h0:sm_seg = 8'b11111111;
     4'h1:sm_seg = 8'b11001111;
     4'h2:sm_seg = 8'b10010010;
     4'h3:sm_seg = 8'b10000110;
     4'h4:sm_seg = 8'b11001100;
     4'h5:sm_seg = 8'b10100100;
     4'h6:sm_seg = 8'b10100000;
     4'h7:sm_seg = 8'b10001111;
     4'h8:sm_seg = 8'b10000000;

    endcase
   end
 always@(disp_dat)
    begin
    case(disp_dat)
      4'h1:sm_bit = 8'b11111110;
    4'h2:sm_bit = 8'b11111101;
    4'h3:sm_bit = 8'b11111011;
    4'h4:sm_bit = 8'b11110111;
    4'h5:sm_bit = 8'b11101111;
    4'h6:sm_bit = 8'b11011111;   
    4'h7:sm_bit = 8'b10111111;
    4'h8:sm_bit = 8'b01111111;
   endcase
   end   
endmodule

60模动态显示计数器


代码：

module led_60dongtai(sys_clk,
                   sys_rstn,
       key_in,
       sm_bit,
       sm_seg,
      
       );
input              sys_clk;
input              sys_rstn;
input              key_in;

reg      [19:0]    delay_cnt;
reg      [19:0]    delay_cnt1;
reg      [7:0]     led;
wire               key_scan;
wire               key_low;
reg                key_samp;
reg                key_samp_r;
reg                key_rst;
reg                key_rst_r;

output   [7:0]     sm_seg;
output   [7:0]     sm_bit;
reg      [7:0]     sm_seg;
reg      [7:0]     sm_bit;
reg      [4:0]     dataout_buf;
reg      [2:0]     disp_dat;

////////按键//////
always@(posedge sys_clk or negedge sys_rstn)
    begin
      if(!sys_rstn)
       key_samp<=1'b1;
  else
      key_samp<=key_in;
  end
always@(posedge sys_clk or negedge sys_rstn)
 begin
      if(!sys_rstn)
       key_samp_r<=1'b1;
  else
      key_samp_r<=key_in;
  end
assign key_scan=key_samp_r&(~key_samp);
always@(posedge sys_clk or negedge sys_rstn)
       begin
     if(!sys_rstn)
      delay_cnt<=20'h0;
   else if(key_scan)
       delay_cnt<=20'h0;
   else
       delay_cnt<=delay_cnt+1'b1;
     end

always@(posedge sys_clk or negedge sys_rstn)
    begin
       if(!sys_rstn)
      key_rst<=1'b1;
   else if(delay_cnt==20'hfffff)
      key_rst<=key_in;
  end
always@(posedge sys_clk or negedge sys_rstn)
     begin
       if(!sys_rstn)
      key_rst_r<=1'b1;
   else
   key_rst_r<=key_rst;
 end
assign key_low=key_rst_r&(~key_rst);

  ///////计数器///////

  always @(posedge sys_clk or negedge sys_rstn)    
    begin  
    
           if(!sys_rstn)   
              led<=4'b0;     
            else  if(key_low)  
              begin  
                 if(led[3:0]==9)      
                   begin   
                     led[3:0]<=0;    
                     if (led[7:4]==5)
                        led[7:4]<=0;
                     else    led[7:4]<=led[7:4]+1;
              end    
               else     
                 led[3:0]<=led[3:0]+1;
               end
     end

  
  
  
  //////显示//////
always@(posedge sys_clk or negedge sys_rstn)
     begin
       if(!sys_rstn)
       delay_cnt1<=16'd0;
   else
       begin
          if(delay_cnt1==16'd49999)
         delay_cnt1<=16'd0;
      else
          delay_cnt1<=delay_cnt1+1'b1;
     end
    end

always@(posedge sys_clk or negedge sys_rstn)
     begin
       if(!sys_rstn)
       disp_dat<=3'd0;
   else
       begin
          if(delay_cnt1==16'd49999)
         disp_dat<=disp_dat+1'b1;
      else
         disp_dat<=disp_dat;
    end
     end
always @(disp_dat)
begin
   case(disp_dat)
   3'b000:
      sm_bit = 8'b1111_1110;
   3'b001:
      sm_bit = 8'b1111_1101;
   default:
      sm_bit = 8'b1111_1110;
 endcase
end

always@(sm_bit)
begin
    case(sm_bit)
      8'b1111_1110:
       dataout_buf=led[7:4];
    8'b1111_1101:
       dataout_buf=led[3:0];
   default:
       dataout_buf=8;
   endcase
end

 always@(dataout_buf)
     begin
       case (dataout_buf)
         4'h0:sm_seg = 8'b00000001;
     4'h1:sm_seg = 8'b01001111;
     4'h2:sm_seg = 8'b00010010;
     4'h3:sm_seg = 8'b00000110;
     4'h4:sm_seg = 8'b01001100;
     4'h5:sm_seg = 8'b00100100;
     4'h6:sm_seg = 8'b00100000;
     4'h7:sm_seg = 8'b00001111;
     4'h8:sm_seg = 8'b00000000;
     4'h9:sm_seg = 8'b00000100;
     4'ha:sm_seg = 8'b00001000;
     4'hb:sm_seg = 8'b00000000;
     4'hc:sm_seg = 8'b00110001;
     4'hd:sm_seg = 8'b00000001;
     4'he:sm_seg = 8'b00110000;
     4'hf:sm_seg = 8'b00111000;
     default:
          sm_seg = 8'b00000001;
    endcase
   end
endmodule
   

明天放假回家，在家有时间一定要赶赶进度。不让版主失望
提前预祝大家新年快乐

近期手上没有摄像机，所以没能上传视频，过段时间再一块上传

 

 

蜂鸣器作业

警笛

参考  http://wenku.baidu.com/view/031ac2630b1c59eef8c7b432.html 

 

代码

 

module jingche(sys_clk,
                sys_rstn,
      beep
      );
input           sys_clk;
input           sys_rstn;
output          beep;

reg             beep;
reg    [22:0]   div_cnt;
reg    [14:0]   delay_cnt;
wire   [14:0]   delay_end;
wire   [6:0]    ramp;

assign          ramp=(div_cnt[22]?div_cnt[21:15]:~div_cnt[21:15]);
assign          delay_end={2'b01,ramp,6'b000000};

always@(posedge sys_clk or  negedge sys_rstn)
begin
     if(!sys_rstn)
       div_cnt<=23'd0;
  else
      div_cnt<=div_cnt+1'b1;
end

 

always@(posedge sys_clk or negedge sys_rstn)
 begin
      if(!sys_rstn)
     delay_cnt<=delay_end;
    else
      if(delay_cnt==15'd0)
    begin
         beep<=~beep;
     delay_cnt<=delay_end;
    end
  else
  delay_cnt<=delay_cnt-1'b1;
end

endmodule