EEPW论坛

这些作业之前已经编好，今天一次性上传,工作比较忙，所以有些简单的就没写注释
功能：显示一个模为60的计数器，即显示从0到59。
视频如下：


视频地址：http://union.bokecc.com/flash/player.swf?vid=592C7C1D59EEBA3A&siteid=290666218ACBA694&playerid=EEA982EE6B20F4D1&playertype=1
代码如下：
module led_scan(clk,
               rst_n,
               SEG,
               DIG);
input clk; //50MHZ
input rst_n; //系统复位，低电平有效
output[7:0] SEG; //段选
output[7:0] DIG; //位选
reg[7:0] SEG; //段选寄输出存器
reg[7:0] DIG; //段选寄输出存器
reg[3:0] num_ge; //个位寄存器
reg[3:0] num_shi; //十位寄存器
reg[7:0] SSEG;  //个位寄存器
reg[7:0] GSEG;  //十位寄存器
reg cnt;   //个十位选
reg[25:0] delay; //计数器
reg[14:0] delay_1k; //刷新频率1KHZ
reg delay_1s;  //1S计数器
//-------------------------------------
initial
 begin
  num_ge<=4'd0;
  num_shi<=3'd0;
  cnt<=1'b0;
 end
always @(posedge clk or negedge rst_n)
 if(!rst_n) delay<=26'd0;
 else
 begin
  if(delay==26'd24999999)
  begin
  delay_1s<=~delay_1s;
  delay<=26'd0;
  end
  else
   begin
   delay<=delay+1'b1;
   end
 end
always @(posedge clk or negedge rst_n)
 if(!rst_n) delay_1k<=15'd0;
 else
 if(delay_1k==15'd4999)
  begin
  cnt<=~cnt;
  delay_1k<=15'd0;
  end
 else
 delay_1k<=delay_1k+1'b1;
//---------------------------------------------------
always@(posedge delay_1s or negedge rst_n)
 if(!rst_n) begin
  num_ge<=4'd0;
  num_shi<=3'd0;
  end
  else
  begin
   if(num_ge==4'd9&&num_shi<3'd5)
   begin
    num_ge<=4'd0;
    num_shi<=num_shi+3'd1;
    end
  else if(num_ge==4'd9&&num_shi==3'd5)
    begin
    num_ge<=4'd0;
    num_shi<=3'd0;
    end
   else
   begin
   num_ge<=num_ge+4'd1;
   end
  end
//-----------------------------------

 
always@(num_ge)
 begin
 case(num_ge)
 4'd0 : SSEG = 8'hc0;   // "0"
 4'd1 : SSEG = 8'hf9;   // "1"
 4'd2 : SSEG = 8'ha4;   // "2"
 4'd3 : SSEG = 8'hb0;   // "3"
 4'd4 : SSEG = 8'h99;   // "4"
 4'd5 : SSEG = 8'h92;   // "5"
 4'd6 : SSEG = 8'h82;   // "6"
 4'd7 : SSEG = 8'hf8;   // "7"
 4'd8 : SSEG = 8'h80;   // "8"
 4'd9 : SSEG = 8'h90;   // "9"
 endcase
 end
always@(num_shi)
 begin
 case(num_shi)
 3'd0 : GSEG = 8'hc0;   // "0"
 3'd1 : GSEG = 8'hf9;   // "1"
 3'd2 : GSEG = 8'ha4;   // "2"
 3'd3 : GSEG = 8'hb0;   // "3"
 3'd4 : GSEG = 8'h99;   // "4"
 3'd5 : GSEG = 8'h92;   // "5"
 3'd6 : GSEG = 8'h82;   // "6"
 /*3'd7 : GSEG = 8'hf8;   // "7"
 3'd8 : GSEG = 8'h80;   // "8"
 3'd9 : GSEG = 8'h90;   // "9"*/
 endcase
 end
always@(cnt)
 begin
  if(cnt) begin
  SEG<=GSEG;
  DIG<=8'hfd;
  end
  if(!cnt) begin
  SEG<=SSEG;
  DIG<=8'hfe;
  end
 end
endmodule