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#ifdef CFG_SDRAM
 /* Initialize the matrix */
 writel(readl(AT91C_BASE_MATRIX + MATRIX_EBICSA) | AT91C_MATRIX_CS1A_SDRAMC, AT91C_BASE_MATRIX + MATRIX_EBICSA);

#ifdef MCK_100
 /* Configure SDRAM Controller */
 sdram_init( AT91C_SDRAMC_NC_9  |
    AT91C_SDRAMC_NR_13 |
    AT91C_SDRAMC_CAS_2 |
    AT91C_SDRAMC_NB_4_BANKS |
    AT91C_SDRAMC_DBW_32_BITS |
    AT91C_SDRAMC_TWR_2 |
    AT91C_SDRAMC_TRC_7 |
    AT91C_SDRAMC_TRP_2 |
    AT91C_SDRAMC_TRCD_2 |
    AT91C_SDRAMC_TRAS_5 |
    AT91C_SDRAMC_TXSR_8,  /* Control Register */
                                (MASTER_CLOCK * 7)/1000000,     /* Refresh Timer Register */
                                AT91C_SDRAMC_MD_SDRAM);         /* SDRAM (no low power)   */

#else /* 133 MHz */
 /* Configure SDRAM Controller */
 sdram_init( AT91C_SDRAMC_NC_9  |
    AT91C_SDRAMC_NR_13 |
    AT91C_SDRAMC_CAS_3 |
    AT91C_SDRAMC_NB_4_BANKS |
    AT91C_SDRAMC_DBW_32_BITS |
    AT91C_SDRAMC_TWR_2 |
    AT91C_SDRAMC_TRC_9 |
    AT91C_SDRAMC_TRP_3 |
    AT91C_SDRAMC_TRCD_3 |
    AT91C_SDRAMC_TRAS_6 |
    AT91C_SDRAMC_TXSR_10,  /* Control Register */
                                (MASTER_CLOCK * 7)/1000000,     /* Refresh Timer Register */
    AT91C_SDRAMC_MD_SDRAM);         /* SDRAM (no low power)   */
#endif