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 answer for question 1:
 在P89CV51RD2 datasheet中有提到：
Comparison to the P89C51RB2/RC2/RD2 devices
SPI interface. The P89CV51RB2/RC2/RD2 devices include an SPI interface that was not present on the P89C51RB2/RC2/RD2 devices.
Smaller block sizes. The smallest block size on the P89C51RB2/RC2/RD2 devices was 4 kB. The P89CV51RB2/RC2/RD2 devices have a page size of 128 B. These small pages can be erased and reprogrammed using IAP function calls making use of the code memory for non-volatile data storage practical. Each page erase is 30 ms or less. The IAP and ISP code in P89CV51RB2/RC2/RD2 devices support these 128-byte page operations. In addition, the IAP and ISP code uses multiple page erase operations to emulate the erasing of the larger block sizes (8 kB and 16 kB to maintain firmware compatibility).
Status bit versus Status byte. The P89C51RD2 device used a Status byte to control the automatic entry into ISP mode following a reset. On the P89CV51RB2/RC2/RD2 devices this has changed to a single Status bit. Since the ISP entry was based on the zero/non-zero value of the Status byte this is an almost identical operation on the P89CV51RB2/RC2/RD2 devices.
Faster block erase. The erase time for the entire user code memory of the P89CV51RB2/RC2/RD2 devices is 150 ms. This is a significant improvement.
More data memory. All devices have 1 kB of RAM compared with the 512 B on the 89C51RB2/RC2 devices.

 answer for question 3:
 都能够很好的兼容89c51架构。CV51RD2更兼容些

 After get the answer of question 2, you may post the answers to that online forum.
 thanks.