请教哪位师兄能帮我看看 一个用modlesim后仿真的问题。 我后仿真的时候输出的一个12位的变量，其中有三位是不定值，其它位都是正常的。 后仿真的时候有警告和报错信息，分别是： Warning: (vsim-3316) No solution possible for some delayed timing check nets. 74 negative limits were zeroed. Error: D:/setted/Xilinx/ISE/verilog/src/simprims/X_FF.v(101): $hold( posedge CLK:1670130 ps, posedge I &&& (in_clk_enable1 != 0):1670220 ps, 152 ps ); # Time: 1670220 ps Iteration: 0 Instance: /tb_TX_MCU/uut/TXPAR_BUF_10 # ** Error: D:/setted/Xilinx/ISE/verilog/src/simprims/X_FF.v(102): $hold( posedge CLK:1803461 ps, negedge I &&& (in_clk_enable1 != 0):1803555 ps, 153 ps ); # Time: 1803555 ps Iteration: 0 Instance: /tb_TX_MCU/uut/TXPAR_BUF_11 # ** Error: D:/setted/Xilinx/ISE/verilog/src/simprims/X_FF.v(101): $hold( posedge CLK:2203457 ps, posedge I &&& (in_clk_enable1 != 0):2203572 ps, 152 ps ); # Time: 2203572 ps Iteration: 0 Instance: /tb_TX_MCU/uut/TXPAR_BUF_14 # ** Error: D:/setted/Xilinx/ISE/verilog/src/simprims/X_FF.v(99): $setup( posedge CE &&& (ce_clk_enable1 != 0):3403406 ps, posedge CLK:3403445 ps, 103 ps ); # Time: 3403445 ps Iteration: 0 Instance: /tb_TX_MCU/uut/TXPAR_BUF_11