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This application note describes a Virtex®-II device implementation of a CSIX-L1 common switch interface between a network processor’s traffic manager and the switching fabric for ATM, IP, MPLS, Ethernet, and similar data communications applications. This design uses a pipeline implementation to achieve a low clock period (approximately 166 MHz), and uses the 32-bit interface CSIX scheme. This document is obsolete/under obsolescence.

xapp289.pdf