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电子产品世界 » 论坛首页 » 嵌入式开发 » FPGA » 【应用笔记】在Stratix III器件中对信号完整性进行I/O设置的影响(Im

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【应用笔记】在Stratix III器件中对信号完整性进行I/O设置的影响(Impact of I/O Settings on Signal Integrity

高工
2012-05-15 09:25:51     打赏

【应用笔记】在Stratix III器件中对信号完整性进行I/O设置的影响(Impact of I/O Settings on Signal Integrity in Stratix III Devices)
这篇应用笔记提供关于对信号质量的I/O设置产生的影响的信息。其主要包括驱动能力和转换速率的影响,并解释了Altera如何定义这两个设置。这些设置包括对已一个给定的I/O以及选择这些基于使用Stratix® III器件的特定应用的方法。
This application note provides information on the effects of the I/O
settings on the quality of the signal. Its main focus is on drive strength
and slew rate effects and explains how Altera® defines these two settings
for a given I/O, along with ways to choose these based on the specific
application for which the Stratix® III device is used.
This application note also covers the impact of multiple topologies,
transmission line lengths, and output loads on the output signal and how
these features relate to the settings mentioned above. This application
note is a technical background document that concludes by providing
recommendations on the selection of the I/O settings based on your
custom system.AN476.pdf




关键词: 应用     笔记     Stratix     器件     信号     完整性         

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