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这是核心板，黑色的，挺好看的

这是接口板，由于TLC5620没整好，改接的时候不小心弄断了一个引脚，等有时间再把它整好

这是整个FPGA DIY的板子，来个集体亮相，呵呵

明天接着写作业，赶进度呀

板子焊完后，测试一下板子，首先做了一个点亮LED
---库函数
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
---实体
entity LED_test is
port(LED:out std_logic_vector(8 downto 1));
end LED_test;
---结构体描述
architecture behave of LED_test is
begin
LED<="10101010";
end behave;

-----流水灯，一共11个LED灯

module water_led(
  input        CLOCK_50,                
  input        Q_KEY,                   // 板载按键RST
  output [11:1] LED                      // LED[1] ~ LED[11]
);   

//++++++++++++++++++++++++++++++++++++++
// 分频部分 开始
//++++++++++++++++++++++++++++++++++++++
reg [23:0] cnt;                         // 计数子
always @ (posedge CLOCK_50, negedge Q_KEY)
  if (!Q_KEY)
    cnt <= 0;
  else
    cnt <= cnt + 1'b1;
 
wire led_clk = cnt[23];                 // 每(2^24/50M = 0.3355)sec取一次

//++++++++++++++++++++++++++++++++++++++
// 流水灯部分 开始
//++++++++++++++++++++++++++++++++++++++
reg [11:1] led_r;                       
reg       dir;                         

always @ (posedge led_clk, negedge Q_KEY)
  if (!Q_KEY)                           
    dir <= 0;                       
  else
     if(led_r == 12'h3FF && dir == 0)
      dir <= 1;
    else if(led_r == 12'h001 && dir == 1)
      dir <= 0;

always @ (posedge led_clk, negedge Q_KEY)
  if (!Q_KEY)                                      
    led_r <= 12'h001;         
  else
     if(!dir)
      led_r <= (led_r << 1) + 1'b1;     
    else
      led_r <= (led_r >> 1);           
assign LED = ~led_r;                   
endmodule

------跑马灯，11个LED灯从左至右依次点亮

module rider_led(
  input        CLOCK_50,                
  input        Q_KEY,                   // 板载按键RST
  output [11:1] LED                      // LED[1] ~ LED[1]
);   

reg [23:0] cnt;                        
always @ (posedge CLOCK_50, negedge Q_KEY)
  if (!Q_KEY)
    cnt <= 0;
  else
    cnt <= cnt + 1'b1;
 
wire led_clk = cnt[23];                 // 每(2^24/50M = 0.3355)sec取一次

reg [11:1]  led_r;                      
reg        dir;                        

always @ (posedge led_clk, negedge Q_KEY)
  if (!Q_KEY)                           // 复位后右移
    dir <= 0;                           
  else
    
    if(led_r[10])                        
      dir <= 1;    
    else if(led_r[2])                   
      dir <= 0;

always @ (posedge led_clk, negedge Q_KEY)
  if (!Q_KEY)                           // 复位后右移
    led_r <= 12'h001;         
  else
       if(!dir)
      led_r <= led_r << 1;              // LED右移
    else   
      led_r <= led_r >> 1;              // LED左移

assign LED = ~led_r;                    // 寄存器输出
endmodule