EEPW论坛

module key_ctrlnum(clk, rstn, key, num);
	input clk, rstn;
	input [6:0] key;
	output [7:0] num;
	
	reg[6:0] key_sample;
	parameter number1=7'b1111111;
	parameter cnt_num=20'hfffff;
	
	
	always@(posedge clk or negedge rstn)
	begin
		if(!rstn)
			key_sample <= number1;
		else
			key_sample <= key;
	end
	
	reg[6:0] key_sample_r;
	
	always@(posedge clk or negedge rstn)
	begin
		if(!rstn)
			key_sample_r <= number1;
		else
			key_sample_r <= key_sample;
	end
	
	wire[6:0] key_an;
	assign key_an = key_sample_r[6:0]&(~key_sample[6:0]);
	
	reg[19:0] cnt;
	
	always@(posedge clk or negedge rstn)
	begin
		if(!rstn)
			cnt <= 20'h0;
		else if(key_an)
			cnt <= 20'h0;
		else
			cnt <= cnt + 1'b1;
	end
	
	reg[6:0] low_sw;
	
	always@(posedge clk or negedge rstn)
	begin
		if(!rstn)
			low_sw <= number1;
		else if(cnt == cnt_num)
			low_sw <= key;
	end
	
	reg[6:0] low_sw_r;
	
	always@(posedge clk or negedge rstn)
	begin
		if(!rstn)
			low_sw_r <= number1;
		else 
			low_sw_r <= low_sw;
	end
	
	wire[6:0] num_ctrl;
	assign num_ctrl = low_sw_r&(~low_sw);
	reg [7:0] num;
	always@(posedge clk or negedge rstn)
	begin
		if(!rstn)
			num <= 8'b11111111;
		else
		begin
			case(num_ctrl)
				7'b1000000: num <= 8'b11111110;
				7'b0100000: num <= 8'b01100000;
				7'b0010000: num <= 8'b11011000;
				7'b0001000: num <= 8'b11110010;
				7'b0000100: num <= 8'b01100110;
				7'b0000010: num <= 8'b10110110;
				7'b0000001: num <= 8'b10111110;
				default: num <= 8'b11111111;
			endcase
		end
	end
endmodule