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library IEEE;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY Msequence is 
PORT(
CLK: IN STD_LOGIC;
OTT: OUT STD_LOGIC
);
end Msequence;

ARCHITECTURE behavior OF Msequence is
SIGNAL a:STD_LOGIC_VECTOR(4 downto 0);
SIGNAL b:STD_LOGIC;
begin

process(CLK)
begin
if rising_edge(CLK) then
b<=(a(0) xor a(3)); 
a(4 downto 0)<=b&a(4 downto 1);

end if;
end process;
OTT<=a(0);
end behavior;
此处参考M序列5阶多项式的生成多项式，x的5次方+x的2次方+1