EEPW论坛

end

这样可以用，但是

always @ (posedge key_out[1]  or posedge key_out[0])
begin
  sum_in <= sum_in +1'b1;

end

附录：程序

module fp (clk,b1,wout,out,key);
input clk;
input [7:0] key;
output [7:0] wout,out;
output b1;
reg [7:0] sum_in;
wire out_ym;
wire [7:0] key_out;
wire key_out1,key_out2;
aj  aj(.in(key),.key_out(key_out),.clk(out_ym)); 
fp1 fb1(.clk(clk),.sum_in(sum_in),.out(b1),.out_ym(out_ym));
ym  ym(.sum_in(sum_in),.out(out),.wout(wout),.clk(out_ym));
initial 
  sum_in = 8'd0;


always @ (posedge key_out[1]  )
begin
  sum_in <= sum_in +1'b1;
end
endmodule