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从sx1212的datasheet(P14)看到如下内容
With an integer-N PLL architecture, the following criterion must be met to ensure correct operation:
.. The comparison frequency, Fcomp, of the Phase Frequency Detector (PFD) input must remain higher than six
times the PLL bandwidth (PLLBW) to guarantee loop stability and to reject harmonics of the comparison
frequency Fcomp. This is expressed in the inequality:
PLLBW ≤ Fcomp/6
.. However the PLLBW has to be sufficiently high to allow adequate PLL lock times
.. Because the divider ration R determines Fcomp, it should be set close to 119, leading to Fcomp≈100 kHz
which will ensure suitable PLL stability and speed.