【简介】
在之前的贴子（【S32K3XX】MCME 启动 CORE1）中core0 通过MCME 把core1 成功的拉起来了，MC_ME集成的功能也比较多，除了上述的启动应用core的功能，MC_ME IP还负责管理时钟控制。从以下的描述可知MC_ME 的管理方式是按照Partition 方式进行管理的。
每个Patition MCME 集成了COFB寄存器来控制时钟的信号。
有了上述的认识我们在回头查看下K3的启动文件的如下代码：
上述的代码是读取 PRTN1_COFB0_STAT 来获取当前MSCM的时钟是否开启，如果未开启则使能对应的时钟，开启MSCM 的时钟是通过MC_ME来进行控制的。从芯片开发手册中也可以找到对应的MSCM 的时钟信号控制在 PRTN1_COFB0 的bit24。
上述代码之所以要开启MSCM的时钟是以为，后续代码要从MSCM读取Core ID,所以要先开启时钟配置。
S32DS 在 POWER mode 配置时可以通过如下的配置来设置外设的时钟信号是否被Gate.
上述配置后生成的代码中会对MC_ME 的3个Patition 生成配置接口提来控制对应外设slot 的时钟Gate 状态。
static const Power_Ip_MC_ME_CofbConfigType Power_Ip_MC_ME_aPartition0CofbConfigPB_0[1U] =
{
/* The configuration structure for Partition 0 COFB 1. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)1U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN0_COFB1_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN0_COFB1_CLKEN_REQ32_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ33_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ34_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ35_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ36_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ38_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ39_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ40_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ41_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ42_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ44_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ45_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ46_MASK | MC_ME_PRTN0_COFB1_CLKEN_REQ47_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN0_COFB1_CLKEN_RWBITS_MASK
}
};
static const Power_Ip_MC_ME_CofbConfigType Power_Ip_MC_ME_aPartition1CofbConfigPB_0[4U] =
{
/* The configuration structure for Partition 1 COFB 0. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)0U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN1_COFB0_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN1_COFB0_CLKEN_REQ3_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ4_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ5_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ6_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ7_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ8_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ9_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ10_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ11_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ12_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ13_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ14_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ15_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ21_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ22_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ23_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ24_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ28_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ29_MASK | MC_ME_PRTN1_COFB0_CLKEN_REQ31_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN1_COFB0_CLKEN_RWBITS_MASK
},
/* The configuration structure for Partition 1 COFB 1. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)1U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN1_COFB1_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN1_COFB1_CLKEN_REQ32_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ33_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ34_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ42_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ45_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ47_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ49_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ51_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ53_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ56_MASK | MC_ME_PRTN1_COFB1_CLKEN_REQ63_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN1_COFB1_CLKEN_RWBITS_MASK
},
/* The configuration structure for Partition 1 COFB 2. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)2U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN1_COFB2_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN1_COFB2_CLKEN_REQ65_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ66_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ67_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ68_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ69_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ70_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ73_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ74_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ75_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ76_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ77_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ78_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ79_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ80_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ81_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ84_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ85_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ86_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ87_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ88_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ89_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ91_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ92_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ93_MASK | MC_ME_PRTN1_COFB2_CLKEN_REQ95_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN1_COFB2_CLKEN_RWBITS_MASK
},
/* The configuration structure for Partition 1 COFB 3. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)3U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN1_COFB3_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN1_COFB3_CLKEN_REQ96_MASK | MC_ME_PRTN1_COFB3_CLKEN_REQ104_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN1_COFB3_CLKEN_RWBITS_MASK
}
};
static const Power_Ip_MC_ME_CofbConfigType Power_Ip_MC_ME_aPartition2CofbConfigPB_0[2U] =
{
/* The configuration structure for Partition 2 COFB 0. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)0U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN2_COFB0_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN2_COFB0_CLKEN_REQ4_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ5_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ6_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ7_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ8_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ9_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ10_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ11_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ12_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ13_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ14_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ15_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ16_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ17_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ18_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ19_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ20_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ21_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ22_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ23_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ24_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ27_MASK | MC_ME_PRTN2_COFB0_CLKEN_REQ29_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN2_COFB0_CLKEN_RWBITS_MASK
},
/* The configuration structure for Partition 2 COFB 1. */
{
/* Specifies whether the given COFB set is under MCU control. */
(boolean)TRUE,
/* The index of the COFB set within the partition. */
(uint8)1U,
/* The clock enable register value of the COFB set. */
MC_ME_PRTN2_COFB1_CLKEN
(
((uint32)0x00000000U) | MC_ME_PRTN2_COFB1_CLKEN_REQ32_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ35_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ36_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ37_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ38_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ39_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ40_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ41_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ42_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ47_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ48_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ51_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ55_MASK | MC_ME_PRTN2_COFB1_CLKEN_REQ58_MASK
),
/* Mask containing the COFB blocks to be updated. */
MC_ME_PRTN2_COFB1_CLKEN_RWBITS_MASK
}
};
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