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仔细看HELP. VHDL和AHDL不一样. 声明是可以COPY的. 应注意的是RAM有 同步和异步两种, 即前者是用时钟的. 但是同步的启动延迟很大, 但适合 PIPELINE操作. 下面给出一个VHDL的简单例子(同步RAM). ---- VHDL --------------- entity EXAMPLE is port ( ... ; ) ; end EXAMPLE ; architecture behave of EXAMPLE is -- 声明一个部件 COMPONENT lpm_ram_dq GENERIC (LPM_WIDTH: POSITIVE; LPM_WIDTHAD: POSITIVE; LPM_FILE: STRING := "UNUSED") ; PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0); address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0); we: IN STD_LOGIC := '1'; inclock: IN STD_LOGIC := '1'; outclock: IN STD_LOGIC := '1'; q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); signal ex_ram_in, ex_ram_out : std_logic_vector(7 downto 0) ; signal ex_ram_ad : std_logic_vector(7 downto 0) ; signal ex_ram_we : std_logic ; begin -- 具体配置一个RAM, 注意RAM初始化文件名应与architecture名保持一致. RAM_EXAMPLE : lpm_ram_dq GENERIC MAP( LPM_WIDTH => 8, LPM_WIDTHAD => 8, LPM_FILE => "EXAMPLE.mif") -- 初始化RAM数据文件 PORT MAP ( data => ex_ram_in, address => ex_ram_ad, we => ex_ram_we, inclock => clk, outclock => clk, q => ex_ram_out ) ; END COMPONENT; -- 对RAM控制信号进行赋值. ex_ram_we <= 赋值语句 ; ex_ram_ad <= 赋值语句 ; -- 或者是由另一个计数器配置生成 ex_ram_in <= 赋值语句 ; -- 或者ex_ram_in本身是PIN -- 下面就可以使用ex_ram_out了. 如 variable_tmp <= ex_ram_out ; end EXAMPLE ;