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Embedded Intel386? processors Programming Flash Memory through the JTAG Port 1.0 Introduction 1.1 Design Motivation 2.0 Background Information 2.1 IEEE 1149.1 - The JTAG Specification 2.1.1 TAPSignal Description 2.1.2 JTAG State Machine 2.2 Intel 386TM EX Embedded Processor JTAG Test-Logic Unit 2.2.1 Boundary Scan Register 2.2.2 Identification Code Register 2.3 Intel 4 Mbit Boot Block Flash 3.0 Sample Design 3.1 TAP Hardware Interface 3.2 JTAG software Interface 3.2.1 Hardware Considerations 3.2.2 Assembly Language Routines 3.2.3 "C" Routines 3.2.4 Program Operation and Options 4.0 Performance Analysis and Considerations 5.0 Conclusion 6.0 Related Information 1.0 Introduction This application note describes a simple method for program ming data into flash memory using a standard JTAG (Joint Test Action Group) port specified by IEEE 1149.1. The JTAG device used in this case is the Inte l386TM EX embedded processor; however, the scope of this application is easi ly extended to many other JTAG compliant devices. Using the features of the Intel386TM EX embedded processor in conjunction with a simple hardware inter face, a standard set of software routines can be used to program data into f lash memory. By controlling the CPU's JTAG port, these routines manage the d ata that is programmed into flash memory as well as the processor's control lines. This document contains a general overview of: The basic functions specified by IEEE 1149.1 The operation of the JTAG port of the Intel386TM EX processor The features of the Intel 28F400BV-T 4-Mbit Boot Block device flash device This application note also provides a functional design which can be used in conjunction with Revision 2.1 of the EV386EX Intel386TM EX Embedded Micropr ocessor Evaluation Board. The design consists of: A simple low-cost parallel port host interface design A standard set of JTAG C++ in-line assembly source code functions Source code that implements the programming, validation, and erasure of the contents of the Boot Block flash device. 1.1 Design Motivation As more packaged silicon devices populate printed circuit boards, the connec tion of test and programming equipment to the fine-pitch IC packages replaci ng socketed, broader-pitch parts becomes less feasible. Furthermore, the des ign of mobile equipment with even smaller form factors and more stringent sh ock tolerance requirements does not allow the designer to use sockets at all . The components in the case must be soldered directly onto the board to red uce manufacturing costs, improve reliability, and decrease the space require d by the hardware. Additionally, Just-In-Time manufacturing requirements mak e it desirable to solder unprogrammed devices, such as flash memory, onto pr inted circuit boards. This allows designers to customize the boards in their final stage, while reducing the amount of inventory that is required by the use or preprogrammed devices. These constraints make the programming of bootstrap software and other firmw are and even more formidable task than in the past. It is now desirable to d ownload these integral pieces of the product into initially unprogrammed mem ories on the board in order to have the microprocessor up and running when i t come time to develop, test and manufacture systems which take advantage of the latest advanced technologies. A good solution is to use a simple flash memory programming device that uses the Test Access Port (TAP) found on JTAG -compliant devices. 2.0 Background Information Designers unfamiliar with the features of the IEEE 1149.1 specification, the Intel386TM EX embedded processor, or the Intel 28F400BV-T Boot Block flash will benefit for a brief overview of the features that these pieces provide. The design for programming flash memory shown in Figure 2 takes advantage o f the features. The design uses: The fire-wire interface of the TAP, which simplifies the hardware requiremen ts. The unique configuration of the Intel386TM EX embedded processor in the embe dded system to control flash memory programming The advanced programming algorithm of the Intel 28F400BV-T Boot Block flash device This application not focuses on the 101-pin JTAG implementation found on the Intel386TM; EX embedded processor. Sections 2.1 and 2.2 describe this imple mentation, while the features of the Boot Block flash device are described i n section 2.3. 2.1 IEEE 1149.1 - The JTAG Specification The IEEE 1149.1 specification was originally intended to provide an easy way to verify the functionality and correct interconnection of both compliant a nd non-compliant devices in a printed circuit board design. However, without the presence of any firmware, the JTAG-compliant Intel386TM EX embedded pro cessor con imitate most of the bus signals by controlling the TAP. This powe rful feature can be used to access all of the peripherals as if an emulator or programmer were connected instead of the CPU. The IEEE's official publication, the IEEE Standard Test Access Port and Boun dary-Scan Architecture, contains a complete description of the JTAG standard and the operation of JTAG-compliant devices. 2.1.1 TAP Signal Descriptions The TAP uses a serial synchronous data exchange protocol and consists of fiv e signals;: TDI- Test Data Input - a serial bit stream that goes into either the JTAG co ntrol/command registers or Boundary Scan Registers (BSR) that control the pi n drivers register on the Intel386TM EX processor. TDO - Test Data Output - a serial bit stream which goes to the tester and co ntains information shifted out of either the identifier register or the Pin Data Capture register of the JTAG unit. TCK - Test Port Clock - a synchronous clock which accompanies any data trans fers through, the JTAG port. Data on input lines is sampled on the rising ed ge of the TCK signal. Data on the output line is sampled on the falling edge of the TCK signal. TMS - Test Mode Select - this signal, used in conjunction with TDI, controls the state machine which determines the state of the TAP-related circuitry a nd the direction of data streams within the device under test. TRST# - Test Port Reset - an optional signal, implemented in the Intel386TM EX processor, that resets the TAP state machine to the predetermined initial state. 2.1.2 JTAG State Machine The movement of data through the TAP can be controlled by supplying the prop er logic level to the TMS pin at the rising edge of consecutive TCK cycles. The TAP controller itself is a finite-state machine that is capable of 15 st ates. Each state contains a link in the operation sequence necessary to mani pulate the data moving throughout the TAP. This includes applying stimuli to the pins, capturing incoming data, loading instructions, and shifting data into and out of the Boundary-Scan Register. Figure 1 shows the TAP state mac hine flowchart, and demonstrates the sequence of inputs on TMS necessary to progress from any one state to another. Asserting the TRST# pin at any time will cause the TAP to reset to the Test-Logic-Reset home state. Figure 1. TAP controller (Finite State Machine) 2.2 Intel 386 EX Embedded Processor JTAG Test-Logic Unit The JTAG Test logic Unit of the Intel386TM EX embedded processor can control all device pins except those of the dock, power, ground and TAP, control si gnals. a boundary scan cell resides at each o f the 101 controlled device pi ns. The cells are corrected serially to form the 101 bit boundary scan regis ter. Each bit has both a control cell, which controls the I/O status of the pin, and a data cell, which holds the logical high or low value to be assert ed at the pin itself. An EXTEST or INTEST instruction, as shown in Table 1, requires a total of 202 (101 bits x 2 cells ) shifts of data into the TAP. In addition to the boundary scan (Bound) register, the Intel386TM EX process or has in instruction register (R) whose instructions are shown in Table 1. These instructions are used in programming flash memory through the JTAG pot . The bypass register (BYPASS) is also featured on the processor, but is onl y used in systems with two ore more JTAG- compliant devices. The identificat ion code (IDCODE) register is the last one implemented in the Intel 3865 Ex processor, and is discussed further in Section 2.2.2. Table 1. Test-Logic Unit Instructions Mnemonic Opcode Description BYPASS 1111 Bypass on-chip system logic (mandatory instruction). Used for th ose components that are not being tested. EXTEST 0000 Off-chip circuitry test (mandatory instruction). Used for testin g device interconnections on a board. SAMPRE 0001 sample pins/preload data (mandatory instruction). Used for contr olling (preload) or observing (sample) the signals at device pins. This test has no effect on system operation. IDCODE 0010 ID code test (optional instruction). Used to identify devices on a board. INTEST 1001 On-chip system test (optional instruction). Used for static test ing of the internal device logic in a single-step mode. HIGHZ 1000 High-impedance/ONCE mode test (optional instruction). Used to pla ce device pins into their inactive drive states. Allows external components to drive signals onto connections that the processor normally drives. Notes: The opcode is the sequence of data bits shifted serially into the instructio n register (IR) from the TDI input. The opcodes for EXTEST and BYPASS are ma ndated by IEEE 1149.1, so they should be the same for all JTAG-compliant dev ices, the remaining opcodes are defined for use on the Intel 38 Ex embedded processor, so they may vary among devices. All unlisted opcodes are reserved. Use or reserved opcodes could cause the d evice to enter reserved factory-test modes. 2.2.1 Boundary Scan Register The order of the bits contained in the Boundary Scan (BSR) is show in Table 2. The direction, or control, bits follow their corresponding data bits in t he chain sequence. For example, Bit 0, M/IO# would be followed in the chain by its directional bit, which in turn would be followed by Bit 1, D/C#. It i s important to remember that the boundary scan register is shifted in serial ly; when shifting data out onto the pins, the first bit shifted into the BSR must be the directional bit of D15 (entry number 100 in Table 2). This meth od ensures that all data is backed onto the correct pins at the conclusion o f the 202 bit serial data shift. Although it is not used in the software example included in Appendix A, a co py of the DSDL (Boundary-Scan Description Language) file for the A and B ste ppings of the Intel 386 Ex embedded processor (JTAGBSDL.ZIP) is located on I ntel's America's Application Support BBS, at (916) 356-3600. This file lists : The physical pin layout of all pins in the Boundary-Scan Register The valid and reserved JTAG unit opcodes. The expected contents of the IDCODE register (shown also in Section 2.2.2) f or the Intel 386TM; EX embedded processor. A description of the BSR contents. The BSDL file may be incorporated into software which uses the JTAG port for testing or programming functions. BSDL is a de-facto standard recently appr oved by the IEEE for describing essential features if IEEE 1149.1(B) complia nt devices. A copy of the Intel 386TM; EX embedded processor BSDL file is sh own in Appendix B. Table 2. Boundary-scan Register Bit Assignments Bit Pin Bit Pin Bit Pin Bit Pin 0 M/IO# 25 A15 50 TMROUT2 75 P2.2 1 D/C# 26 A16/CAS0 51 TMRGATE2 76 P2.3 2 W/R# 27 A17/CAS1 52 INT4/TMRCKL0 77 P2.4 3 READY# 28 A18/CAS2 53 INT5/TMRGATED 78 DACK0# 4 BS8# 29 A19 54 INT6/TMRCLK1 79 P2.5/RXD0 5 RD# 30 A20 55 INT7/TMRGATE1 80 P2.6/TXD0 6 WR# 31 A21 56 STXCLK 81 P2.7 7 BLE# 32 A22 57 FLT# 82 UCS# 8 BHE# 33 A23 58 P1.0 83 CS6#/REFRESH# 9 ADS# 34 A24 59 P1.1 84 LBA# 10 NA# 35 A25 60 P1.2 85 D0 11 A1 36 SMI# 61 P1.3 86 D1 12 A2 37 P3/0/TMROUT0 62 P1.4 87 D2 13 A3 38 P3.1/TMROUT1 63 P1.5 88 D3 14 A4 39 SRXCLK 64 P1.6/HOLD 89 D4 15 A5 40 SSIORX 65 RESET 90 D5 16 A6 41 SSIOTX 66 P1.7/HLDA 91 D6 17 A7 42 P3.2/INT0 67 DACK1#/TXD1 92 D7 18 A8 43 P3.3/INT1 68 EOP# 93 D8 19 A9 44 P3.4/INT2 69 WDTOUT 94 D9 20 A10 45 P3.4/INT3 70 DRQ0 95 D10 21 A11 46 P3.6/WRDOWN 71 DRQ1/RXD1 96 D11 22 A12 47 P3.7/SERCLK 72 SMIACT# 97 D12 23 A13 48 PEREQ/TMRCLK2 73 P2.0 98 D13 24 A14 49 NMI 74 P2.1 99 D14 Notes: 1 Bit 0 is closest to TDI; bit 100 is closest to TDO. 2 The boundary-scan chain consists of 101 bits; however, each bit has both a control cell and a data cell, so an EXTEST or INTEST instruction requires 2 02 shifts (101 bits ` 2 cells). 2.2.2 Identification Code Register The IDCODE instruction allows the user to determine the contents of the devi ce's identification code register. For the Intel386TM EX embedded processor this command should return one of the values shown in Table 3. Table 3. Device Identification Codes Step VCC IDCODE A 5 V 0027 0013H B 5 V 0027 0013H C 5 V 2027 0013H C 3 V 2827 0013H For more information about identification codes, see the Intel386TM EX embed ded Microprocessor User's Manual. 2.3 Intel 4 Mbit Boot Block Flash The number of instructions necessary to program flash devices is significant ly reduced by using an Intel Boot Block device. In the sample design describ ed in the next section. the automated Write State Machine (WSM) of the 28F40 0BV-T flash unit ensures that all algorithms and timings necessary for erasi ng and programming the device are executed automatically, freeing the TAP co ntrol software of additional burdensome I/O cycles and iterative code. The d evice also performs its own program and erase verifications, updating the St atus Register (SR) to indicate the successful completion of operations. Thes e features are standard with Intel's Boot Block, FlashFileTM; and Embedded F lash RAM families, which are available in a variety of sizes and configurati ons. Writing data to Intel's second-generation flash memories consists of these s teps: 1. The write setup command (40H) is issued to flash memory. 2. This is followed by a second write specifying the address and data for th e location to be written. 3. The data and address are latched internally on the rising edge of the WE# strobe, which may be issued by one of a variety of sources At this point, the WSM takes over, writing the results of the verification i nto the status register. Since data access is much slower than the typical p rogramming time, the contents of the SR need not be checked after each write . Instead, writes are repeated sequentially for all locations to be programm ed, with the SR verified when the block programming is completed. After the device is programmed, the data may be read back sequentially with RD# held c onstantly low, and the contents may be verified by comparison against the so urce code. The static nature of the Intel386? Ex embedded processor's Boundary Scan Reg ister outputs combined with the high speed of the flash device ensures that timing issues are a minimal problem. In fact, a 16 bit word may be written t o the flash device in only a single cycle of the boundary scan register. Thi s is accomplished by using an additional output pin of the controlling PC's parallel port connected to WE# to clock the data and address into the chip. By doing so, as is discussed in Section 4.0, Performance Analysis and Consid erations, even a simple design can achieve throughput levels of more than 1 Kbyte per second through the serial BSR of the Test Access Port. 3.0 Sample Design 3.1 TAP Hardware Interface Figure 2 illustrates a straightforward design that uses a standard parallel port to communicate with the TAP of the Intel386TM EX Embedded Microprocesso r Evaluation Board. This interface is typical on any design based on the Int el386TM EX embedded processor, and requires only a CMOS buffer to protect th e TAP pins and translate the printer port signals to the CMOS levels require d for the TAP. This assembly can be built onto a simple cable or card that p lugs into the Intel386TM EX embedded Microprocessor Evaluation Board Option Header. It receives power and ground signals form the Evaluation Board, whic h must be powered on during operation of the TAP programmer. The majority of the signal control is done by software routine which read and write data to and from the BSR. Figure 2 TAP Parallel Port Interface 3.2 JTAG Software Interface This section details the operation of the various software routines that use the Test Access Port to program data into the Boot Block flash. The source code for the executable program. TAPLOADR.EXE which contains both inline ass embly routines as well as C language functions, is shown in Appendix A. The software demonstrates how t Configure and modify the status of pins for data input and output Shift in the values necessary to perform I/O to the flash device Perform operations such as status checks and data I/O 3.2.1 Hardware Considerations The high-level routines used in programming data through the TAP are device- dependent because they assume a particular device configuration on the board as well as a predetermined system interface. In the example, the JTAG chain contains only a single IEEE 1149.1 compliant device, the Intel386TM EX embe dded processor. If the JTAG chain consisted of several devices connected in series, the routine would need to control the whole chain and place any othe r devices into the BYPASS mode. The routines in the example assume only a si ngle device with separate RD# and WR# strobes generated by the CPU. The WR# signal may be enabled externally to improve performance; this is discussed i n Section 4.0, Performance Analysis and Considerations. Several preparations must be made before the flash memory can be programmed. On the Evaluation Board, JP12 must be installed and R12 removed. Jumpering pins 1 and 2 of JP12 enables the PWD signal (pin 44) of the 28F400BV-T flash device, which provides programming voltage for block erases and writes. Whe n programming the flash, is also critical to enable VPP (Pin 1) by setting P ort 1.5 (pin 107) of the Intel386TM EX embedded processor on the Evaluation Board used in the example. In the example, UCS# is used as the chip select (CS#) for the flash device; is LOW for any address that is accessed. The example also implies static beh avior of the bus; therefor, the connection of flash chips to the CPU should be independent of any clocks. If any buffers on the busses are required in t he design, their direction and enable signals should be static. Take care to ensure that all flash control signals are clock-independent. Revision 2.1 o f the EV386 EX Intel386TM EX Embedded Microprocessor Evaluation Board requir es that a change be made to temporarily disconnect the output of Pin 20 of t he U 16 PLD (FLASH_WE#) so that the flash's ;WE# signal may be controlled by an external, static, and clock-independent source. Examples are shown in Fi gure 2 for Parallel Port and TAP control of the WE# signal. Making the chang es described in the figure notes enables the correct operation of the progra mming functions and eliminates any contention for control of the devices and their signals. Future steppings of the Intel386TM EX embedded processor remove the need for PLD control of the flash's WE# signal by correcting errata #29 of the Intel 386 Ex embedded processor errata list. This allows a glue-less flash interf ace to be used in some designs and eliminates the need for modifications to the PLD when implementing the programming of the flash memory through the TA P. When cutting the trace on the FLSH_WE# signal, however, care must be take n to jumper pins 3-4 on the JTAG interface card so that correct operation of the EV386EX evaluation board is retained. Although two examples are given for resetting the JTAG unit of the Intel386T M EX embedded processor, it is only necessary to use one of the provided mea ns to return the TAP state machine to Test-Logic-Reset. If the chosen implem entation uses the Restore_Idle function rather than the Reset_JTAG routine, it is advisable to tie an inverted CPU Reset signal to the TRST# input of th e processor. This guarantees that the TAP relinquishes control of all the co ntrolled CPU pins upon a system reset. If the Reset_JTAG function is used, c are must be taken to reset the system immediately after TRST# is asserted. 3.2.2 Assembly Language Routines The heart of the software that allows you to program flash through the JTAG port is contained in the assembly routines which control the JTAG unit of th e Intel 386 EX embedded processor via the parallel port of a PC. These routi nes have been implemented as inline assembly code to simplify the developmen t process and the clarity of the software. They use a set of bit masks and v ariables shown in the first section of Appendix A under the heading "Assembl y Language Variables.: A description of each function is shown below. Reset-JTAG- Resets the TAP to the Test-Logic-Reset state by toggling the TRS T# signal. This signal is optional in IEEE 1149.1, but has been provided on the Intel386TM EX embedded processor. Alternately, the same function is prov ide by five consecutive TCK periods with TMS held high. See Restor_Idle (bel ow) for more details. Restore_Idle - Resets the TAP to the Test-Logic-Reset state by transitioning through the state machine. TMS is held high for five consecutive TCK clock periods. This is in accordance with the IEEE 1149.1 specification. TMS_High - Provides a vehicle for progression through the state machine with TMS held high for a single TCK clock period. Used when shifting data into a nd out of the TAP. TMS_Low - Provides a vehicle for progression through the state machine with TMS held low for a single TCK clock period. Used when shifting data into and out of the TAP. Shift_Data_Array - Shifts a data string into the TAP while copying the data in the TAP into the place of the incoming data. This function is called when the TAP state machine is the Select_DR_Scan state. Shift_Data_Array_In - Shifts a data string into the TAP and does not copy an y data form the TAP in the place of the incoming data. This function is call ed when the TAP state machine is in the Select_DR_Scna state. Strobe_Data_In - Pluses the STROBE# line of the PC's parallel port. This fun ction is used only when STROBE# is connected to the WE# line of the flash. 3.2.3 "C" Routines Appendix A contains a number of "C" language functions that make the program ming of flash modular and easy to implement. Many of them are called from th e "Main" function of TAPLOADR.EXE, but others are used to move data back and forth into the TAP by means that would be complicated by using assembly lan guage programming. The program was complied under MicrosoftTM; Visual C++ 1. 50. A list of the functions, their dependencies, and a brief description of their operation is given below. Send_Instruction - Sends a JTAG instruction as a string into the TAP. Replac es the original string with the data that is shifted out on TDO. Send_Instruction_IN - Sends a JTAG instruction as a string into the TAP. Doe s not replace the original string with the data that is shifted out on TDO. Send_Data- Sends a JTAG data string into the TAP. Replaces the original stri ng with the data that is shifted out on TDO. Send_Data_In - Sends a JTAG data string into the TAP. Does not replace the o riginal string with the data that is shifted out on TDO. Flip_ID_String - Flips the JTAG unit ID string within its own array. This ne eds to be done in order to reverse the string which is read in backwards, le ast significant bit first. This allows for verification of the data that is read against the value shown in the Intel386TM EX embedded Microprocessor Us er's Manual most significant bit first. Get_JTAG_Device_ID - Retrieves the JTAG device ID from the processor. Displa ys the results and the expected value. Fill_JTAG - Initializes the values in the 202 bit JTAG BSR array for a stand ard configuration. Sets up input and output pins and values for the control pins in the BSR. Sets the direction bits of the unused pins to a value of "0 " which makes them inputs. This routine is unique to the Intel386TM EX embed ded processor and must be configured differently for other devices. Set_Data - Decodes a 16 bit data word onto the Do through D15 data lines in the BSR array. Sets the data line directional bits to a value of "1" which m akes them into outputs. Used when writing data to the flash. Get_Data - Configures the data lines as inputs, allowing data to be output f orm the flash and read into the BSR array. Used when reading data back form flash. Parse_Data - Reads the data from the data lines in the BSR array and parses into to a 16 bit data word. Used when reading data back from the flash. Set_Address - Decodes an address onto the A12 through A25 data lines in the BSR array. Sets the directional bits for the address lines to a value of "1" which makes them into outputs. Used for both reads and writes to and from t he flash. Flash_Read - Reads a 16 bit data word to the flash device at the specified a ddress. Used for data programming and status checks. Used for verification o f data and status checks. Flash_Write - Writes a 16 bit data word to the flash device at the specified address. Used for data programming and status checks. Optional section with in this procedure may be chosen depending on chosen method of WE# hardware c ontrol. Only one type of WE# signal enabling procedure may be used at a time . Input_File_Name_OK - Verifies that the input file is a file that can be read . When this function does not return a value of TRUE, the program displays a n error message and prompts the user to try executing the program again. If the file is valid, the program executes normally. Get_Flash_Device_ID - Retrieves the flash device ID from the Intel Boot Bloc k flash Device. Displays the results and the expected value. Check_Flash_Status - Clears the flash status registers and sends a Read Stat us command to the device. The results are read back and displayed along with the expected values for a properly functioning device. Erase_Flash - Erases each block within the Intel Boot Block flash device. An address within each block is stored in an array in this function, and the f unction loops for a specified number of blocks, seven in this case. The func tion may be altered to erase only the Boot Block or selected blocks within t he device. Program_Flash_Data - Outputs data from the specified binary input file to th e flash device. Data is read in as 8-bit characters and is merged into 16-bi t words which are then written to the Flash device. Status checks are not pe rformed after each write, because doing so slows performance. The function d isplays the status of a successful programming operation and notifies the us er if the input file has been closed successfully. Read_Flash_Data- Reads back the data that has been written to the flash into the file VERIFY.BIN. A file comparison may be done to check the correct pro gramming of flash data. This in unnecessary in most real applications, but i n marginally faster than checking status after each word is programmed. 3.2.4 Program Operation and Options TAPLOADR.EXE operations are controlled form the program's "Main" function. T he program does not execute until it is given a valid input file name. Table 4 lists the functions which verify, write, and then read back the data in t he file that is written to the flash device. Table 4. TAPLOADER.EXE Order of Execution Input_File_Name_OK (input_file) //Checks input file name Fill_JTAG(Pin State); //Initialization string Reset_JTAG(); //Reset the JTAG unit Restore_Idle(); //used to reset JTAG state machine Get_JTAG_Device_ID(); //Get ID -see 386 EX manual for code Get_Flash_Device_ID(); //Get Id - see flash manual Check_Flash_Status(); //Check status register example Erase_Flash(); //Erases the entire flash chip i = Program_Flash_Data(); //Opens file and programs flash data Check_Flash_Status(); //Checks status before continuing Read_Flash_Data ("verify.bin", data_start-address, i); //Copy contents to fi le The program displays status check messages throughout its operation. It is i mportant to recognize that some operations, especially when programming larg e amounts of data, may take from a few seconds to a few minutes to complete. A block erase operation normally requires approximately 0.5 seconds per blo ck, or about 4 seconds per flash device. Writing data may take from just a f ew seconds to over 30 minutes, depending on the size of the input file and t he methods used for verifying data programming and enabling WE# on the flash chip. These issues are discussed in the next section. 4.0 Performance Analysis and Considerations A number of factors can affect the performance, specifically the throughput levels , of any programming device that uses the JTAG port. Among, these, th e most critical are the methods used to write the data into the flash device and verify that it has been successfully stored at the correct location. As was mentioned earlier, reducing the number of status checks performed whi le programming can greatly reduce the time required to program data into fla sh, The relatively slow operation of the parallel port and TAP combination e nsures that read and write operations do not interfere with those that prece de them. Checking status bits only at the end of blocks or writes can reduce programming time by as much as on half. Table 5 shows a comparison of typic al timings measures while loading data into the flash device found on the In tel386TM EX Embedded Microprocessor Evaluation Board. Table 5. TAP Flash Programming Sample Timings 32Kbyte Write Yes WE# 180 5.62 32Kbyte Read NA WE# 40 1.25 32Kbyte Write No WE# 100 3.12 32Kbyte Read NA WE# 40 1.25 32Kbyte Write No STROBE# 45 1.41 32Kbyte Read NA STROBE# 40 1.25 512Kbyte Write Yes WE# 2940 5.74 512Kbyte Read NA WE# 660 1.28 512Kbyte Write No WE# 1620 3.16 512Kbyte Read NA WE# 660 1.28 512Kbyte Write No STROBE# 555 1.08 512Kbyte Read NA STROBE# 590 1.15 Table 5 also illustrates how the use of a WE# generated by the STROBE# line of a typical parallel port may expedite the delivery of data through the TAP . Using this method allows writes to complete in a single cycle of the TAP, rather than the normal three cycles that are required when strobing the WE# signal from the TAP. As shown in Appendix A, the data and address are placed on the bus in a single cycle when using STROBE# line externally. in the lat ter case, however, three complete shifts of the BSR data must be performed i n order to send the data and address and simultaneously toggle the WE# line in a similar high-low-high pattern. Reductions in write cycle time of close to two thirds are expected when using the first method. The unused data sign als of the parallel port may also be used to control other useful signals su ch as RD#, or to monitor the status of control lines on the system under tes t. It is worth mentioning that several companies currently offer JTAG port inte rface cards that use a standard ISA bus interface to communicate with one or more Test Access Ports. These cards can vastly improve the data transfer ra tes of about .05 Kbytes per second that are typical of a parallel port progr ammer. Although this rate is comparable to that of a typical EPROM programme r, TMS periods on the order of a few microseconds are less than ideal. Typic al data rates of 8 Mbits per second by be achieved by a simple card which us es RAM to send and read data patterns from the JTAG port. Since the bus sign al emulation requires only the toggling of a few signals out of all that are within the BSR, the card stores the data to be written and transfers it to the TAP in a rapid manner. Most hardware vendors provide a library of softwa re to assist the programmer in writing code to interface with such cards. Ev en the simplest combination of hardware and software can be a valuable tool in programming and testing new code in flash. 5.0 Conclusion The Intel386TM EX processor provides a powerful means of programming onboard flash devices to meet the needs of Just-In-Time manufacturing systems. Unpr ogrammed devices may now be soldered directly onto PCB/s allowing for concur rent software and hardware development processes as well as last minute chan ges in BIOS code without the loss of valuable time or inventory. Accessing t hese devices via the chip's IEEE 1149.1-compliant Test Access Port provides an inexpensive, versatile, and reliable tool that functions far beyond the r ealms of debug and test. If shock-tolerance and reduction of form-factor are primary design concerns, using the JTAG port is sure to be an important too l for in-circuit device reprogramming and reconfiguration. The parallel port of a standard PC becomes a flexible tool in this case, and may be used to g enerate TAP signals for either lab or low-volume production. With a high-per formance solution based on a simple TAP controller card in a PC, programming performance significantly improves without the purchase of costly test equi pment. 6.0 Related Information This application note is one of the may sources of information available reg arding designing with the Intel386TM EX embedded processor. Table 6 shows ot her useful documents and their Intel order numbers. Table 6. Related Intel Documents Publication Title Order Number Intel386TM EX Embedded Microprocessor datasheet 272420 Intel386TM EX Embedded Microprocessor User's Manual 272485 Intel386TM SX Embedded Microprocessor datasheet 240187 Intel386TM SX Embedded Microprocessor Programmer's Reference Manual 240331 Intel386TM SX Embedded Microprocessor Hardware Reference Manual 240332 186 Development Tools Handbook 272326 Intel386TM EX Embedded Microprocessor Evaluation Board Manual 272525 Buyers Guide for the Intel386TM EX Embedded Processor Family 272520 Packaging 240800 1995 Flash Memory Databook 210830 To receive these documents or any other available Intel literature, contact: