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Verilog HDL常见问题

菜鸟
2007-03-29 20:13:35     打赏

问题:在使用case语句建模组合逻辑的时候,综合工具提示会出现latch
原因:产生这个错误时候可以从下面三个方面检查:
1. 看看这个语句块的敏感列表是否完备,也就是是否所有的“输入”信号都位于敏感列表内;
2. case语句是否覆盖了所有可能的条件;
3. “输出”信号是否在每个分支上都进行了赋值操作;
例如:
always @(sel or in1 or in2) begin
case (sel)
2'b00 : begin // out2在这个分支没有赋值
out1 = in1;
end
2'b01 : begin
out2 = in2;
end
default : begin
out1 = in1;
out2 = in2;
end
endcase
end

引申:实际上这个问题还经常出现在使用if...else建模组合逻辑当中。

问题:如何使用Verilog语言描述一个双向口。
答案:

对双向口,我们可以将其理解为2个分量:一个输入分量,一个输出分量。另外还需要一个控制信号控制输出分量何时输出。此时,我们就可以很容易地对双向端口建模。

例子:


CODE:
module dual_port (
....
inout_pin,
....
);

inout inout_pin;

wire inout_pin;

wire input_of_inout;
wire output_of_inout;
wire out_en;

assign input_of_inout = inout_pin;

assign inout_pin = out_en ? output_of_inout : z;

endmodule
可见,此时input_of_inout和output_of_inout就可以当作普通信号使用了。

在仿真的时候,需要注意双向口的处理。如果是直接与另外一个模块的双向口连接,那么只要保证一个模块在输出的时候,另外一个模块没有输出(处于高阻态)就可以了。
如果是在ModelSim中作为单独的模块仿真,那么在模块输出的时候,不能使用force命令将其设为高阻态,而是使用release命令将总线释放掉。


问题:4‘b1011&&4'b0100=?? 结果应该是多少啊?

答案:
上面的运算结果为1。&&是逻辑与操作,4'b1011不为0,因此它的逻辑值为“真”,同样的原因4'b0100的逻辑值也为“真”,因此逻辑与的结果为“真”,根据Verilog-2001:

1 (defined as true), 0 (defined as false),


因此问题的操作结果为1。

引申:
Verilog-2001中有关逻辑操作符的描述:

4.1.9 Logical operators

The operators logical and (&&) and logical or (||) are logical connectives. The result of the evaluation of a logical comparison shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value (x). The precedence of && is greater than that of ||, and both are lower than relational and equality operators.

A third logical operator is the unary logical negation operator (!). The negation operator converts a nonzero or true operand into 0 and a zero or false operand into 1. An ambiguous truth value remains as x.

Examples:

Example 1—If reg alpha holds the integer value 237 and beta holds the value zero, then the following examples perform as described:

regA = alpha && beta; // regA is set to 0
regB = alpha || beta; // regB is set to 1

Example 2—The following expression performs a logical and of three subexpressions without needing any parentheses:

a < size-1 && b != c && index != lastone

However, it is recommended for readability purposes that parentheses be used to show very clearly the precedence intended, as in the following rewrite of this example:

(a < size-1) && (b != c) && (index != lastone)

Example 3—A common use of ! is in constructions like the following:

if (!inword)

In some cases, the preceding construct makes more sense to someone reading the code than this equivalent construct:

if (inword == 0)




关键词: Verilog     常见问题     inout    

菜鸟
2007-03-29 20:44:00     打赏
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