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如下是写的一段发脉冲的程序，功能都是可以实现的，只是觉得是不是代码写得不好所以占用的资源较多，比如if判断太多了，希望大大们看看给点建议

module  pulse(sclk, over,DATA, DATA_LAST,diff,dire, AbsErr_flag, rest);
   input sclk;            //10M时钟
   input over;            //一次数据读取（含校验）结束标志，结束后维持一周期（0.4us）高电平
   input [16:0] DATA;     
   input [16:0] DATA_LAST;   
   input [6:0] AbsErr_flag;
   input rest;
   output diff;           
   output dire;          
   
   wire diff;            
   wire sclk;
   reg dire;
   reg [23:0] difcount;      
   reg exclude_flag;
 
    assign diff = ((difcount)&&(~over))?sclk:1'b0;   

 //脉冲输出，输出difcount个sclk(脉冲)
   always @(posedge over or negedge sclk or negedge rest)//(over|sclk))  
   begin
     if(rest == 1'b0)
     begin
        difcount = 24'd0;
     end
     else
     begin
          if(over)                           //上升沿只一次  
          begin 
             if((AbsErr_flag[6:3] == 0)&&exclude_flag) 
             begin
                 if(DATA > DATA_LAST)
                 begin        
                     if((~(DATA_LAST[16]|DATA_LAST[15]))&(DATA[16]&DATA[15]))
                     begin
                         dire =1'b0;
                         difcount = 24'h20000-DATA+DATA_LAST;
                     end
                     else
                     begin
                         dire = 1'b1;               
                         difcount = DATA-DATA_LAST;       
                     end
                 end
                else 
                begin    
                    if((~(DATA[16]|DATA[15]))&(DATA_LAST[16]&DATA_LAST[15])) 
                    begin
                        dire =1'b1;
                        difcount = 24'h20000-DATA_LAST+DATA;
                    end        
                    else
                    begin
                    dire = 1'b0;             
                    difcount = DATA_LAST-DATA;
                    end
                end 
          end           
      end  
    else 
    begin 
           difcount <= (difcount)?(difcount-1'b1):0; //difcount自减至0 
    end    
  end
end

always @(negedge over or negedge rest)
begin
 if(rest == 1'b0)
 begin  
     exclude_flag = 0;
 end
 else
 begin
      exclude_flag = 1;  
 end
end  

endmodule

这段代码加到主工程里多占了200多的逻辑单元，但是拿出来建工程编译后看好像没那么多。另外附上warnings:

Warning (10240): Verilog HDL Always Construct warning at pulse.v(23): inferring latch(es) for variable "dire", which holds its previous value in one or more paths through the always construct

Warning: Node "pulse:inst|dire" is a latch

Info: Assuming node "rest" is a latch enable. Will not compute fmax for this pin.

Info: Detected gated clock "pulse:inst|always0~1" as buffer
Info: Detected ripple clock "pulse:inst|exclude_flag" as buffer
Info: Detected gated clock "pulse:inst|always0~0" as buffer
Info: Detected ripple clock "pulse:inst|difcount[23]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[22]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[21]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[20]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[19]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[18]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[17]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[16]" as buffer
Info: Detected gated clock "pulse:inst|WideOr0~3" as buffer
Info: Detected ripple clock "pulse:inst|difcount[15]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[14]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[13]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[12]" as buffer
Info: Detected gated clock "pulse:inst|WideOr0~2" as buffer
Info: Detected ripple clock "pulse:inst|difcount[11]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[10]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[9]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[8]" as buffer
Info: Detected gated clock "pulse:inst|WideOr0~1" as buffer
Info: Detected ripple clock "pulse:inst|difcount[7]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[6]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[5]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[4]" as buffer
Info: Detected gated clock "pulse:inst|WideOr0~0" as buffer
Info: Detected ripple clock "pulse:inst|difcount[3]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[2]" as buffer
Info: Detected ripple clock "pulse:inst|difcount[1]" as buffer
Info: Detected gated clock "pulse:inst|WideOr0~6" as buffer
Info: Detected gated clock "pulse:inst|WideOr0~5" as buffer
Info: Detected ripple clock "pulse:inst|difcount[0]" as buffer
Info: Detected ripple clock "send:inst12|AbsErr_flag[3]" as buffer
Info: Detected ripple clock "send:inst12|AbsErr_flag[4]" as buffer
Info: Detected ripple clock "send:inst12|AbsErr_flag[5]" as buffer
Info: Detected ripple clock "send:inst12|AbsErr_flag[6]" as buffer
Info: Detected ripple clock "send:inst12|over" as buffer
Info: Detected gated clock "pulse:inst|dire~3" as buffer
Info: Detected gated clock "pulse:inst|diff" as buffer
Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock "sclk" with clock skew larger than data delay. See Compilation Report for details.