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用fpga实现分频

kaisadadi33
菜鸟
2014-04-05 21:17:42     打赏
要实现波特率范围从 9.6  kb/s到 12 Mb/s，共分 9 档这个功能，用fpga内的PLL可以实现不？我看用Cyclone EP1C的好像只能输出两个供内部使用的时钟。能不能给个设计思路呢？？用fpga内的锁相环数量多的话会对fpga工作的稳定性造成影响不
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关键词： fpga     分频    


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xqh518
院士
2014-04-05 23:50:28     打赏
2楼
学习了，有待消化 ，谢谢楼主。

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jobs
院士
2014-04-06 12:02:47     打赏
3楼

印象中，我是使用高频率的主频，然后再使用简单的分频功能，将不同频率输出至不同的引脚，最终实现的不同频率的输出功能。

——话说 好久不弄FPGA了~~


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kaisadadi33
菜鸟
2014-04-06 17:33:31     打赏
4楼
哦，为啥不做FPGA了？？现在做什么呢，主要是为了采集数据，数据发送的波特率有9中情况，看资料说是用PLL比较精确，就想看能用PLL实现不。顺带问一下，有没有波特率自检测方面的设计资料啊？？求助。。

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kaisadadi33
菜鸟
2014-04-06 17:33:50     打赏
5楼
客气

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jobs
院士
2014-04-07 10:50:44     打赏
6楼
波特率自检的方法比较多。 我写过在ARM下识别串口波特率的文章，在网站的“牛人业话”里，可以参考 

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lianggui5
工程师
2014-04-07 13:12:18     打赏
7楼
楼主是在做串口通信吧，， 一般都是高频去分哈，然后采样可以用高速时钟去采样哈。。 有一定的时钟偏差时允许的，只要不是偏的太离谱，一般都不会错。 跟单片机差不多哈，单片机也是用Timer去实现的，所以FPGA里面也是用计数器哈， 不用PLL，而且PLL一般输出不了9Khz，这么低的频率哈

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