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电子钟VHDL设计

高工
2014-06-12 10:37:42    评分

电子钟VHDL设计

电子钟VHDL设计

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1.系统设计要求
(1)具有时、分、秒计数显示功能,小时为24进制,分钟和秒为60进制。
(2)可以根据需要设置复位、清零、置位等功能。
2.系统设计方案概述
根据系统设计要求,系统设计采用自顶向下设计方法,由秒计数模块、分计数模块、时计数模块、时间设置模块和译码模块五部分组成。
3.参考VHDL源程序
(1)秒计数模块的VHDL源程序(second.vhd)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysecondis
port(clk,reset,semin:instd_logic;
enmin:outstd_logic;
daout:outstd_logic_vector(6downto0));
endsecond;
architecturertlofsecondis
signalcount:std_logic_vector(6downto0);
signalenmin_1,enmin_2:std_logic;
begin
daout=count;
enmin_2=(seminandclk);
enmin=(enmin_1orenmin_2);
process(clk,reset,semin)
begin
if(reset='0')then
count="0000000";
enmin_1='0';
elsif(clk'eventandclk='1')then
if(count(3downto0)="1001"then
if(count16#60#)then
if(count="1011001"then
enmin_1='1';count="0000000";
else
count=count+7;
endif;
else
count="0000000";
endif;
elsif(count16#60#)then
count=count+1;
enmin_1='0';
else
count="0000000";enmin_1='0';
endif;
endif;
endprocess;
endrtl;
仿真:
(2)分计数模块VHDL程序(minute.vhd)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityminuteis
port(clk,reset,clks,sethour:instd_logic;
enhour:outstd_logic;
daout:outstd_logic_vector(6downto0));
endminute;
architecturertlofminuteis
signalcount:std_logic_vector(6downto0);
signalenhour_1,enhour_2:std_logic;
begin
daout=count;
enhour_2=(sethourandclk);
enhour=(enhour_1orenhour_2);
process(clk,reset,sethour)
begin
if(reset='0')then
count="0000000";
enhour_1='0';
elsif(clk'eventandclk='1')then
if(count(3downto0)="1001"then
if(count16#60#)then
if(count="1011001"then
enhour_1='1';count="0000000";
else
count=count+7;
enhour_1='0';
endif;
else
count="0000000";
endif;
elsif(count16#60#)then
count=count+1;
enhour_1='0'after100ns;
else
count="0000000";enhour_1='0';
endif;
endif;
endprocess;
endrtl;
仿真
(3)时计数模块VHDL源程序(hour.vhd)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityhouris
port(clk,reset:instd_logic;
daout:outstd_logic_vector(5downto0));
endhour;
architecturertlofhouris
signalcount:std_logic_vector(5downto0);
begin
daout=count;
process(clk,reset)
begin
if(reset='0')then
count="000000";

elsif(clk'eventandclk='1')then
if(count(3downto0)="1001"then
if(count16#23#)then
count=count+7;
else
count="000000";
endif;
elsif(count16#23#)then
count=count+1;
else
count="000000";
endif;
endif;
endprocess;
endrtl;
仿真
(4)时间设置模块VHDL程序(settime.vhd)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitysettimeis
port(clk,reset:instd_logic;
sec,min:instd_logic_vector(6downto0);
hour:instd_logic_vector(5downto0);
dp:outstd_logic;
sel:outstd_logic_vector(5downto0);
daout:outstd_logic_vector(3downto0));
endsettime;
architecturertlofsettimeis
signalcount:std_logic_vector(2downto0);
begin
process(clk,reset)
begin
if(reset='0')then
count="000";
elsif(clk'eventandclk='1')then
if(count>="101"then
count="000";
else
count=count+1;
endif;

endif;
endprocess;
process(clk,reset)
begin
if(reset='0')then
daout="0000";
dp='0';
sel="111111";
elsif(clk'eventandclk='1')then
casecountis
when"000"=>daout=sec(3downto0);
dp='0';
sel="111110";
when"001"=>daout(3)='0';
daout(2downto0)=sec(6downto4);
dp='0';
sel="111101";
when"010"=>daout=min(3downto0);
dp='1';
sel="111011";
when"011"=>daout(3)='0';
daout(2downto0)=min(6downto4);
dp='0';
sel="110111";
when"100"=>daout=hour(3downto0);
dp='1';
sel="101111";
when"101"=>daout(3downto2)="00";
daout(1downto0)=hour(5downto4);
dp='0';
sel="011111";
whenothers=>daout="0000";
dp='0';
sel="111111";
endcase;
endif;
endprocess;
endrtl;
仿真
(5)译码显示模块的VHDL程序(deled.vhd)
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydeledis
port(num:instd_logic_vector(3downto0);
led:outstd_logic_vector(6downto0));
enddeled;
architecturertlofdeledis
begin
led="1111110"whennum="0000"else
"0110000"whennum="0001"else
"1101101"whennum="0010"else
"1111001"whennum="0011"else
"0110011"whennum="0100"else
"1011011"whennum="0101"else
"1011111"whennum="0110"else
"1110000"whennum="0111"else
"1111111"whennum="1000"else
"1111011"whennum="1001"else
"1110111"whennum="1010"else
"0011111"whennum="1011"else
"1001110"whennum="1100"else
"0111101"whennum="1101"else
"1001111"whennum="1110"else
"1000111"whennum="1111";
endrtl;



关键词: VHDL    

菜鸟
2016-07-02 22:46:51    评分
2楼
请问那个semin是代表什么呢?enmin是秒的进位输出吧,enmin_2=(seminandclk);
enmin=(enmin_1orenmin_2);这两行又是什么意思呢?刚接触VHDL,看的不是很明白

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