EEPW论坛

本坛Jason_zhang很是高手，等待他与你好好讨论下

当然还有个新ID了

叫xilinxeepw，呵呵

看这名字就知道了

    I read the xilinx’s constraint guide, it said that Tin_before>=Tdata+Tsu-Tclk,      we knew the Tin_before is good as large as possible for a fixed device that we can do nothing.       the question is that the designing FPGA device receives the data from other device when we use the DATA_IN_BEFORE to set the constraints,so the Tin_before is a known characteristic,we can get it using the oscilloscope. Using Tin_before to set the Tdata is our purpose,so optionally choosing a large Tin_before that is larger than Tdata+Tsu-Tclk maybe get larger Tdata,result in failure for latching data.my guess is that setting small Tin_before characteristic can get small Tdata,so can latch correct data.       So is the constraint book wrong, or my thought wrong ?   When we want to set the constraint, how do we estimate the period,DATA_IN_BEFORE,DATA_OUT_AFTER?   Which characteristics do we need to get from the FPGA datasheet ?    And,when we set the global constraints,because have IOB’s setup and CLB’s setuptime,which characteristic do we choose ?   How to set the FF ot FF timing,like setup/hold time ? use FROM_TO’s TS_C2S ?    And,because both IOB and CLB have FFs, their FFs setup/hold time characteristics are different, so how to estimate the FFs’s timing ?          Expect the reply,thanks everybody    

以上问题我用英文写了一份到国外论坛求教，描述可能清楚一点。论坛好像不能付附件，可惜。

可以上传附件的。
就在发帖时编辑框的最后一行倒数第二个那个蓝白相间的图标，点击就可以打开“分享下载”，按提示操作就可以了。

和你们一起学习