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交通灯主频：40mhz;红灯、绿灯：50s;黄灯：10s  双管计数
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity traffic is
    Port ( rst : in std_logic;
           clk : in std_logic;
           ledout : out std_logic_vector(7 downto 0);
           ledk : out std_logic_vector(5 downto 0);
           ledA : out std_logic_vector(7 downto 0));
end traffic;

architecture Behavioral of traffic is
signal  count: std_logic_vector(7 downto 0);
signal countt: std_logic_vector(26 downto 0);
signal countn: std_logic_vector(15 downto 0);
signal ledat:  std_logic_vector(3 downto 0);
signal ledmove:std_logic;
type  st  is(westg,westy,southg,southy);
signal my_st:st;
begin
 process(clk,rst)
    begin
     if  rst='0'then
      countt<=(others=>'0');
      countn<=(others=>'0');
      ledmove<='0';
     elsif rising_edge(clk) then
       if  countt=39999999 then
        countt<=(others=>'0');
        countn<=countn+1;
      else
        countt<=countt+1;
        countn<=countn+1;
      end if;
        if  countn(15)='1' then
            countn<=(others=>'0');
            ledmove<= not ledmove;
    
  end if;
  end if;
  end process;
process(clk,rst)
  begin
    if rst='0' then
     count<="01001001";
     my_st<=westg;
     ledout<=not "00001100";
    elsif  rising_edge(clk) then
       case my_st is
         when  westg=>
           ledout<=not "00001100";
         if count=0 then
          count<="00001001";
          my_st<=westy;
           elsif  countt=39999999 then
                  count<=count-1;
      my_st<=westg;
      elsif count(3 downto 0)="1111"then
         count(3 downto 0)<=count(3 downto 0)-6;
  end if;
         when  westy=>
               ledout<=not "00010100";
          if count=0 then
            count<="01001001";
            my_st<=southg;
          elsif countt=39999999 then
            count<=count-1;
            my_st<=westy;
          end if;
        when  southg=>
            ledout<=not "00100001";
         if count=0 then
           count<="00001001";
           my_st<=southy;
         elsif countt=39999999 then
           count<=count-1;
           my_st<=southg;
   elsif count(3 downto 0)="1111" then
      count(3 downto 0)<=count(3 downto 0)-6;
   -- end if;
         end if;
       when southy=>
          ledout<=not "00100010";
          if count=0 then
           count<="01001001";
           my_st<=westg;
          elsif countt=39999999 then
            count<=count-1;
            my_st<=southy;
           end if;
       when others=>
           my_st<=southg;
           ledout<=not "00100001";
           count<="00001000";
      end case;
    end if;
   end process;
process(clk,rst)
  begin
    if rst='0' then
       ledk<="000011";
      elsif rising_edge(clk) then
        case ledmove is
            when '0' =>
              ledk<=not "111101";
              ledat<=count(3 downto 0);
            when '1'=>
              ledk<=not "111110";
              ledat<=count(7 downto 4);
            when others=>
              ledk<="111111";
              ledat<=(others=>'0');
       end case;
 end if;
end process;
process(ledat)
 begin
   case ledat is
         when"0000"=>
         ledA<=x"3f";
        when"0001"=>
         ledA<=x"06";
        when"0010"=>
         ledA<=x"5B";
        when"0011"=>
         ledA<=x"4F";
        when"0100"=>
         ledA<=x"66";
       when"0101"=>
         ledA<=x"6D";
       when"0110"=>
        ledA<=x"7D";
       when"0111"=>
        ledA<=x"07";
    when"1000"=>
        ledA<=x"7F";
     when"1001"=>
        ledA<=x"6F";
    when others=>
        ledA<=x"00";
 end case;
 end process;

end Behavioral;

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