EEPW论坛

3-15

15: 

LRBRAR IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BJQ7 IS

PORT (INPUT: IN STD_LOGIC_VECTOR(6 DOWNTO 0;

OUTPUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

Y: OUT STD_LOGIC;

END BJQ7;

ARCHITECTURE BHV OF BJQ7 IS

BEGIN

PROCESS(INPUT)

VARIABLE Q : STD_LOGIC_VECTOR(2DOWNTO 0);

BEGIN

Q :=”000”;

FOR n in 0 TO 6 LOOP

IF (INPUT(n)=’1’) THEN Q:=Q+1;

END IF;

END LOOP;

OUTPUT<=Q;

IF (OUTPUT>=4) Y<=’1’ ELSE Y<=’0’;

END IF;

END PROCESS