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3-5   1：条件赋值语句：

LIBRARY    IEEE;

USE  IEEE.SID_LOGIC_1164.ALL;

USE  IEEE.SID_LOGIC_UNSIGNED.ALL;

ENTITY(DIN:IN    STD_LOGIC_VECTOR(2  DOWNTO  0);

       DOUT:OUT    BIT_VECTOR(7  DOWNTO  0));

END   DECODER  3  TO  8;

ARCHICTURE  BHV  OF  DECODER  3  TO  8 IS

BEGIN

    WITH  CONV_INTEGER(DIN)SELECT

DOUT<=  “00000001”  WHEN 0,

DOUT<=  “00000010”  WHEN 1,

DOUT<=  “00000100”  WHEN 2,

DOUT<=  “00001000”  WHEN 3,

DOUT<=  “00010000”  WHEN 4,

DOUT<=  “00100000”  WHEN 5,

DOUT<=  “01000000”  WHEN 6,

DOUT<=  “10000000”  WHEN 7;

UNAFFECTER    WHEN   OTHERS;

END  BHV;

2：CASE语句：

LIBRARY    IEEE;

USE  IEEE.SID_LOGIC_1164.ALL;

USE  IEEE.SID_LOGIC_UNSIGNED.ALL;

ENTITY(DIN:IN    STD_LOGIC_VECTOR(2  DOWNTO  0);

       DOUT:OUT    BIT_VECTOR(7  DOWNTO  0));

END   DECODER  3  TO  8;

ARCHICTURE  BHV  OF  DECODER  3  TO  8 IS

BEGIN

  PROCESS(DIN)

  BEGIN

       CASE  CONV_INTEGER(DIN)  IS

       WHEN  0=> DOUT <= “00000001”;

       WHEN  1=> DOUT <= “00000010”;

       WHEN  2=> DOUT <= “00000100”;

       WHEN  3=> DOUT <= “00001000”;

       WHEN  4=> DOUT <= “00010000”;

       WHEN  5=> DOUT <= “00100000”;

       WHEN  6=> DOUT <= “01000000”;

       WHEN  7=> DOUT <= “10000000”;

       WHEN   OTHERS => NULL;

       END   CASE;

   END  PROCESS;

END   BHV;

3：if   else  语句：

LIBRARY    IEEE;

USE  IEEE.SID_LOGIC_1164.ALL;

USE  IEEE.SID_LOGIC_UNSIGNED.ALL;

ENTITY(DIN:IN    STD_LOGIC_VECTOR(2  DOWNTO  0);

       DOUT:OUT    BIT_VECTOR(7  DOWNTO  0));

END   DECODER  3  TO  8;

ARCHICTURE  BHV  OF  DECODER  3  TO  8 IS

BEGIN

  PROCESS(DIN)

  BEGIN

IF CONV_INTEGER(DIN)=0  THEN DOUT<= “00000001”;

ELSIF CONV_INTEGER(DIN)=1  THEN DOUT<= “00000010”;

ELSIF CONV_INTEGER(DIN)=2  THEN DOUT<= “00000100”;

ELSIF CONV_INTEGER(DIN)=3  THEN DOUT<= “00001000”;

ELSIF CONV_INTEGER(DIN)=4  THEN DOUT<= “00010000”;

ELSIF CONV_INTEGER(DIN)=5  THEN DOUT<= “00100000”;

ELSIF CONV_INTEGER(DIN)=6  THEN DOUT<= “01000000”;

ELSIF CONV_INTEGER(DIN)=7  THEN DOUT<= “10000000”;

    END   IF;

   END  PROCESS;

END  BHV;

4：移位操作法：

LIBRARY    IEEE;

USE  IEEE.SID_LOGIC_1164.ALL;

USE  IEEE.SID_LOGIC_UNSIGNED.ALL;

ENTITY(DIN:IN    STD_LOGIC_VECTOR(2  DOWNTO  0);

       DOUT:OUT    BIT_VECTOR(7  DOWNTO  0));

END   DECODER  3  TO  8;

ARCHICTURE  BHV  OF  DECODER  3  TO  8 IS

BEGIN

DOUT<= “00000001”SLLCONV_INTEGER(DIN);

END   BHV;

3-14   七人表决器：

LRBRAR   IEEE;

USE  IEEE.STD_LOGIC_1164.ALL;

ENTITY  BJQ7 IS

PORT  (INPUT:  IN  STD_LOGIC_VECTOR(6 DOWNTO 0;

      OUTPUT:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

       Y: OUT     STD_LOGIC）;

END  BJQ7;

ARCHITECTURE  BHV  OF BJQ7  IS

BEGIN

PROCESS(INPUT)

VARIABLE  Q : STD_LOGIC_VECTOR(2DOWNTO 0);

BEGIN 

Q :=”000”;

FOR n in  0  TO  6  LOOP

  IF (INPUT(n)=’1’)  THEN Q:=Q+1;

 END IF;

END  LOOP;

OUTPUT<=Q;

IF (OUTPUT>=4)  Y<=’1’  ELSE Y<=’0’;

END  IF;

END PROCESS

END ARCHITECTURE BHV