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5-1.

同步复位和异步复位。同步复位是指与 时钟同步 ，当复位信号有效之后，出现时钟有效边沿时才对电路模块进行复位操作;而异步复位与 时钟信号 无关，只要复位信号有效，无论这时时钟信号是什么样，都对电路模块进行复位操作。

同步复位 D触发器 :

IF clock'event AND clock='1' THEN

IF reset_n='0' THEN q <= (OTHERS => '0');

ELSE q <= d;

END IF;

END IF;

异步复位D触发器:

IF reset_n='0' THEN q <= (OTHERS => '0');

ELSIF clock'event AND clock='1' THEN q <= d;

END IF;

5-7.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT10 IS

PORT(CLK,RST,EN,LOAD : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

COUT : OUT STD_LOGIC);

ARCHITECTURE behav OF CNT10 IS

BEGIN

PROCESS(CLK,RST,EN,LOAD)

VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0);

BEGIN

IF RST='0' THEN Q:=(OTHERS =>'0');

ELSIF CLK'EVENT AND CLK='1' THEN

IF EN='1' THEN

IF LOAD='0' THEN Q:=DATA;

ELSE

IF Q<9 THEN Q:=Q+1;

ELSE Q:=(OTHERS=>'0');

END IF;

END IF;

END IF;

END IF;

IF Q=9 THEN COUT<='1';

ELSE COUT<='0';

END IF;

DOUT<=Q;

END PROCESS;

5-8.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ADD_SUB_LOAD_16 IS

PORT (CLK,RST,ADD_EN,SUB_EN,LOAD : IN STD_LOGIC;

DATA:IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;

CQ : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;

COUT:OUTSTD_LOGIC);
EN D ENTITY ADD_SUB_LOAD_16;
ARCHITECTUREA_S_16OFADD_SUB_LOAD_16IS
BEGIN

PROCESS(CLK,RST,ADD_EN,SUB_EN,LOAD)
VARIABLECQI:STD_LOGIC_VECTOR(15DOWNTO0);
VARIABLELS_LOAD:

STD_LOGIC;
BEGINLS_LOAD:=LOAD;
IFRST='1'THENCQI:=(OTHERS=>'0');

ELSIF LOAD='1'THENCQI:=DATA;--LS_LOAD:='0';

ELSIF CLK'EVENTANDCLK='1'THEN 
IF ADD_EN='1'THEN

IF CQI<16#FFFF#THECQI:=CQI+1; 
ELSE CQI:=(OTHERS=>'0');

EN D IF;
I F CQI=16#FFFF#THENCOUT<='1'; 
ELSE COUT<='0';
END IF; 
END IF; 
IF SUB_EN='1'THEN 
IF CQI>0 THEN CQI:=CQI-1; 
ELSE CQI:=(OTHERS => '1'); 
END IF; 
IF CQI=0 THEN COUT<='1'; 
IF CQI=0 THEN COUT<='1';

IF CQI=0THENCOUT<='1';

CQ<=CQI;

ENDPROCESS;
END ARCHITECTURE A_S_16;