EEPW论坛

CASE语句

LRBRAR   IEEE;

USE  IEEE.STD_LOGIC_1164.ALL;

ENTITY  YMQ3to8 IS

PORT  (  DIN: IN  STD_LOGIC_VETOR(2 DOWNTO 0;   

DOUT : OUT  BIT_VECTOR(7 DOWNTO 0);

END  YMQ38;

ARCHITECTURE BHV OF YMQ38 IS

BEGIN

 PROCESS(DIN)

BEGIN

  CASE CONV_TNTEGER(DIN) IS

WHEN 0=>DOUT<=”00000001”;

WHEN 1=>DOUT<=”00000010”;

WHEN2=>DOUT<=”00000100”;

WHEN 3=>DOUT<=”00001000”;

WHEN 4=>DOUT<=”00010000”;

WHEN 5=>DOUT<=”00100000”;

WHEN 6=>DOUT<=”01000000”; 

WHEN 7=>DOUT<=”10000000”;

WHEN OTHERS =>NULL

END  CASE;

条件赋值语句

LRBRAR   IEEE;

USE  IEEE.STD_LOGIC_1164.ALL;

ENTITY  YMQ3to8 IS

PORT  (  DIN: IN  STD_LOGIC_VETOR(2 DOWNTO 0;   

DOUT : OUT  BIT_VECTOR(7 DOWNTO 0);

END  YMQ38;

ARCHITECTURE BHV OF YMQ38 IS

BEGIN

 PROCESS(DIN)

BEGIN

  WITH CONV_TNTEGER(DIN)  SECLET

  DOUT<=”00000001”WHEN 0,

         ”00000010”WHEN 1,

         ”00000100”WHEN2,

         ”00001000”WHEN3,

         ”00010000”WHEN4,

         ”00100000”WHEN5,

         ”01000000”WHEN6

         ”10000000”WHEN 7,

NAFFECTED WHEN OTHERS;

END BHV

IF_ELSE语句

LRBRAR   IEEE;

USE  IEEE.STD_LOGIC_1164.ALL;

ENTITY  YMQ3to8 IS

PORT  (  DIN: IN  STD_LOGIC_VETOR(2 DOWNTO 0;   

DOUT : OUT  BIT_VECTOR(7 DOWNTO 0);

END  YMQ38;

ARCHITECTURE BHV OF YMQ38 IS

BEGIN

IF   CON_INTEGER(DIN)=0 THEN DOUT<=”00000001”;

ELSIF CON_INTEGER(DIN)=1 THEN DOUT<=”00000010”

ELSIF CON_INTEGER(DIN)=2 THEN DOUT<=”00000100”

ELSIF CON_INTEGER(DIN)=3 THEN DOUT<=”00001000”

ELSIF CON_INTEGER(DIN)=4 THEN DOUT<=”00010000”

ELSIF CON_INTEGER(DIN)=5 THEN DOUT<=”00100000”

ELSIF CON_INTEGER(DIN)=6 THEN DOUT<=”01000000”

ELSIF CON_INTEGER(DIN)=7THEN DOUT<=”10000000”

END IF;

END PROCESS;

END BHV

移位操作

LRBRAR   IEEE;

USE  IEEE.STD_LOGIC_1164.ALL;

ENTITY  YMQ3to8 IS

PORT  (  DIN: IN  STD_LOGIC_VETOR(2 DOWNTO 0;   

DOUT : OUT  BIT_VECTOR(7 DOWNTO 0);

END  YMQ38;

ARCHITECTURE BHV OF YMQ38 IS

BEGIN

  DOUT<=”00000001” SLL CONV_INTEGR(DIN);

END BHV

第十五题：

LRBRAR   IEEE;

USE  IEEE.STD_LOGIC_1164.ALL;

ENTITY  BJQ7 IS

PORT  (INPUT:    IN    STD_LOGIC_VECTOR(6 DOWNTO 0;

       OUTPUT:   OUT  STD_LOGIC_VECTOR(2 DOWNTO 0);

       Y:         OUT     STD_LOGIC;

END  BJQ7;

ARCHITECTURE  BHV  OF BJQ7  IS

BEGIN 

PROCESS(INPUT)

VARIABLE  Q : STD_LOGIC_VECTOR(2DOWNTO 0);

BEGIN  

Q :=”000”;

FOR n in  0  TO  6  LOOP

  IF (INPUT(n)=’1’)  THEN Q:=Q+1; 

 END IF;

END  LOOP;

OUTPUT<=Q;

IF (OUTPUT>=4)  Y<=’1’  ELSE Y<=’0’;

END  IF;

END PROCESS

END ARCHITECTURE BHV