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ISIM 中如何观察内部（或定义的中间）信号

比如

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity test1 is
 port( clk : in std_logic;
 count:out std_logic_vector(3 downto 0));
end test1;

architecture Behavioral of test1 is
--signal fcount : integer range 1 to 24000000 :=1;
signal fcount : integer range 1 to 10 :=1;
signal count_tmp: std_logic_vector(3 downto 0):="0000";
signal clk1 : std_logic :='0';

begin
process(clk)
 begin
 if clk'event and clk = '1' then
 if fcount = 10 then 
 fcount <= 1;
 clk1 <= not clk1;
 else 
 fcount <= fcount+1;
 end if;
 end if;
 end process;
 
process(clk1)
 begin
 if clk1'event and clk1 = '1' then
 if count_tmp = "1001" then 
 count_tmp <= "0000";
 else 
 count_tmp <= count_tmp+1;
 end if;
 end if;
 end process;
 count <= count_tmp;
end Behavioral;

	

 如何在 ISIM 中观测 fcount，count_tmp,clk1 信号