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异步复位D触发器

library ieee;
use ieee.std_logic_1164.all;
entity ggg is
port(D,clk,clr:in std_logic;
Q:out std_logic);
end entity ggg;
architecture one of ggg is
begin
process(clk,D,clr)
begin
if clk'event and clk='1' then
if clr='1' then
Q<='0';
else
Q<=D;
end if;
end if;
end process;
end architecture one;

library ieee;
use ieee.std_logic_1164.all;
entity ggg is
port(D,clk,clr:in std_logic;
Q:out std_logic);
end entity ggg;
architecture one of ggg is
begin
process(clk,D,clr)
begin
if clr='1' then
Q<='0';
elsif clk'event and clk='1' then
Q<=D;
end if;
end process;
end architecture one;

与门电路

library ieee;
use ieee.std_logic_1164.all;
entity ggg is
port(a,b:in std_logic;
c:out std_logic);
end ggg;
architecture one of ggg is
begin
c<=a and b;
end one;

非门电路

library ieee;
use ieee.std_logic_1164.all;
entity ggg is
port(a:in std_logic;
b:out std_logic);
end ggg;
architecture one of ggg is
begin
b<=not a;
end one;

vhdl 全减器

----------------------------------------------------
-- 全减器 --
----------------------------------------------------
entity full_sub is
port(x, y : in bit;--std_logic;
sub_in : in bit;--std_logic;--低借位
diffr : out bit;--std_logic; --差
sub_out: out bit);--std_logic);--高借位
end entity full_sub;
----------------------------------------------------
--
architecture b of full_sub is
begin
process(x,y,sub_in) is
subtype std3bit is bit_vector(0 to 2);
begin
case std3bit'(x&y&sub_in) is
when "000" => diffr <= '0'; sub_out <= '0';
when "001" => diffr <= '1'; sub_out <= '1';
when "010" => diffr <= '1'; sub_out <= '1';
when "011" => diffr <= '0'; sub_out <= '1';
when "100" => diffr <= '1'; sub_out <= '0';
when "101" => diffr <= '0'; sub_out <= '0';
when "110" => diffr <= '0'; sub_out <= '0';
when "111" => diffr <= '1'; sub_out <= '1';
end case;
end process;
end architecture b;
-----------------------------------------------------

-----------------------------------------------------
--结构化描述
architecture str of full_sub is
signal tempD, tempC1,tempC2 :bit;
component half_sub
port(x, y : in bit;
d, c : out bit);
end component;
component orgate
port(x, y : in bit;
z : out bit);
end component;
begin
u0: half_sub port map(x,y,tempD,tempC1);
u1: half_sub port map(tempD,sub_in,diffr,tempC2);
u2: orgate port map(tempC1,tempC2,sub_out);
end architecture str;
-----------------------------------------------------
--配置
configuration xw of full_sub is
for b
end for;
end configuration xw;
configuration jgh of full_sub is
for str
end for;
end configuration jgh;

-----------------------------------------------------
-----------------------------------------------------
--半减器
-----------------------------------------------------
entity half_sub is
port(x,y : in bit;
d,c : out bit); --d 差,c 高借位
end entity half_sub;
architecture a of half_sub is
begin
process(x,y)
begin
d <= x xor y;
c <=(not x) and y;
end process;
end architecture a;
-----------------------------------------------------
-----------------------------------------------------
--或门
-----------------------------------------------------
entity orgate is
port(x,y : in bit;
z : out bit);
end entity orgate;
architecture a of orgate is
begin
z<= x or y;
end architecture a;
-----------------------------------------------------
-----------------------------------------------------

vhdl 七段译码器

library ieee;
use ieee.std_logic_1164.all;

entity bcdtoled is
port(bcd : in std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0));--(6:0 is a,b,c,d,e,f,g);
end entity bcdtoled;

architecture a of bcdtoled is
begin
with bcd select
led <= "1111110" when "0000",
"0110000" when "0001",
"1101101" when "0010",
"1111001" when "0011",
"0110011" when "0100",
"1011011" when "0101",
"1011111" when "0110",
"1110000" when "0111",
"1111111" when "1000",
"1111011" when "1001",
"1110111" when "1010",
"0011111" when "1011",
"1001110" when "1100",
"0111101" when "1101",
"1001111" when "1110",
"1000111" when "1111",
"0000000" when others;

end architecture a;

这可是初学者的福音啊

建议斑竹能够给予加精