5、VGA八色显示
视频:
源码:
module veg_8_colour(
clk,rst_n,
hsync,vsync,
vga_r,vga_g,vga_b
);
input clk; //50MHz
input rst_n; //低电平复位
output hsync; //行同步信号
output vsync; //场同步信号
output vga_r;
output vga_g;
output vga_b;
//--------------------------------------------------
reg[10:0] x_cnt; //行坐标
reg[9:0] y_cnt; //列坐标
always @ (posedge clk or negedge rst_n)
if(!rst_n) x_cnt <= 11'd0;
else if(x_cnt == 11'd1039) x_cnt <= 11'd0;
else x_cnt <= x_cnt+1'b1;
always @ (posedge clk or negedge rst_n)
if(!rst_n) y_cnt <= 10'd0;
else if(y_cnt == 10'd665) y_cnt <= 10'd0;
else if(x_cnt == 11'd1039) y_cnt <= y_cnt+1'b1;
//--------------------------------------------------
wire valid; //有效显示区标志
assign valid = (x_cnt >= 11'd187) && (x_cnt < 11'd987)
&& (y_cnt >= 10'd31) && (y_cnt < 10'd631);
wire[9:0] xpos,ypos; //有效显示区坐标
assign xpos = x_cnt-11'd187;
assign ypos = y_cnt-10'd31;
//--------------------------------------------------
reg hsync_r,vsync_r; //同步信号产生
always @ (posedge clk or negedge rst_n)
if(!rst_n) hsync_r <= 1'b1;
else if(x_cnt == 11'd0) hsync_r <= 1'b0; //产生hsync信号
else if(x_cnt == 11'd120) hsync_r <= 1'b1;
always @ (posedge clk or negedge rst_n)
if(!rst_n) vsync_r <= 1'b1;
else if(y_cnt == 10'd0) vsync_r <= 1'b0; //产生vsync信号
else if(y_cnt == 10'd6) vsync_r <= 1'b1;
assign hsync = hsync_r;
assign vsync = vsync_r;
//--------------------------------------------------
//对行进行8等分,显示8个区间
//用红蓝绿及三种颜色的叠加使得显示8种颜色
wire a_dis,b_dis,c_dis,d_dis,e_dis,f_dis,g_dis,h_dis;
assign a_dis = ( (xpos>=0 ) && (xpos<=100) );
assign b_dis = ( (xpos>=100) && (xpos<=200) );
assign c_dis = ( (xpos>=200) && (xpos<=300) );
assign d_dis = ( (xpos>=300) && (xpos<=400) );
assign e_dis = ( (xpos>=400) && (xpos<=500) );
assign f_dis = ( (xpos>=500) && (xpos<=600) );
assign g_dis = ( (xpos>=600) && (xpos<=700) );
assign h_dis = ( (xpos>=700) && (xpos<=800) );
//--------------------------------------------------
//r,g,b控制液晶屏颜色显示
//a显示红色
//b显示绿色
//c显示蓝色
//d区间为红绿叠加 显示黄色
//e区间为红蓝叠加 显示紫色
//f区间为蓝绿叠加 显示天蓝色
//h区间没有任何颜色 显示黑色
assign vga_r = valid ? (a_dis | d_dis | e_dis | g_dis) : 1'b0;
assign vga_g = valid ? (b_dis | d_dis | f_dis | g_dis) : 1'b0;
assign vga_b = valid ? (c_dis | e_dis | f_dis | g_dis) : 1'b0;
endmodule
sof文件:http://share.eepw.com.cn/share/download/id/79019