前段时间很忙,耽误了一段时间,现在上传数码管的显示程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_Unsigned.ALL;
ENTITY showseg7 IS
PORT(clk_p: IN STD_LOGIC;
dig:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--数码管选择输出引脚
seg:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--数码管段输出引脚
END ENTITY showseg7;
ARCHITECTURE one OF showseg7 IS
SIGNAL count: STD_LOGIC_VECTOR(2 DOWNTO 0);--定义数码管输出寄存器
SIGNAL seg_r: STD_LOGIC_VECTOR(7 DOWNTO 0);--定义数码管选择输出寄存器
SIGNAL dig_r: STD_LOGIC_VECTOR(7 DOWNTO 0);--定义显示数据寄存器
SIGNAL disp_r:STD_LOGIC_VECTOR(2 DOWNTO 0);--定义计数寄存器
BEGIN
PROCESS(clk_p)
BEGIN
IF RISING_EDGE(clk_p) THEN
IF count="111" THEN count<="000";
ELSE count<=count+1;
END IF;
END IF;
END PROCESS;
PROCESS(count)
BEGIN
CASE count IS
WHEN "000" => disp_r<="000";dig_r<="01111111";seg_r<="11000000";--显示0
WHEN "001" => disp_r<="001";dig_r<="10111111";seg_r<="11111001";--显示1
WHEN "010" => disp_r<="010";dig_r<="11011111";seg_r<="10100100";--显示2
WHEN "011" => disp_r<="011";dig_r<="11101111";seg_r<="10110000";--显示3
WHEN "100" => disp_r<="100";dig_r<="11110111";seg_r<="10011001";--显示4
WHEN "101" => disp_r<="101";dig_r<="11111011";seg_r<="10010010";--显示5
WHEN "110" => disp_r<="110";dig_r<="11111101";seg_r<="10000010";--显示6
WHEN "111" => disp_r<="111";dig_r<="11111110";seg_r<="11111000";--显示7
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
seg<=seg_r;
dig<=dig_r;
END ARCHITECTURE one;