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模60计数器 http://v.youku.com/v_show/id_XNDkyMzgwNjQ0.html 源码 module cnt60(sys_clk , sys_rstn , sm_seg , sm_bit ); input sys_clk ; input sys_rstn ; output [7:0] sm_seg ; output [7:0] sm_bit ; reg [7:0] sm_seg ; reg [7:0] sm_bit ; reg [25:0] delay_a ; reg [7:0] g ; reg [7:0] s ; reg delay_1s ; reg delay_1ms ; reg [15:0] delay_b ; reg [3:0] num_g ; reg [3:0] num_s ; always@(posedge sys_clk or negedge sys_rstn) begin if(!sys_rstn) delay_a

版主，为什么我的源码贴上去很乱呢？

 module cnt60(sys_clk                 ,
                           sys_rstn               ,
                           sm_seg               ,
                           sm_bit       
                           );
input                           sys_clk        ;
input                           sys_rstn      ;
output    [7:0]             sm_seg      ;
output    [7:0]             sm_bit         ;

reg       [7:0]               sm_seg       ;
reg       [7:0]               sm_bit          ;
reg       [25:0]             delay_a        ;
reg       [7:0]               g                    ;
reg       [7:0]               s                    ;
reg                   delay_1s                 ;
reg                   delay_1ms             ;
reg       [15:0]      delay_b               ;
reg       [3:0]       num_g                 ;
reg       [3:0]       num_s                 ;

always@(posedge sys_clk or negedge sys_rstn)
begin
    if(!sys_rstn)
       delay_a<=26'd0;
    else
       begin
           if(delay_a==26'd24999999)
              begin
              delay_1s<=~delay_1s;
              delay_a<=26'd0;
              end
           else
               delay_a<=delay_a+1'b1;
       end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
    if(!sys_rstn)
       delay_1ms<=16'd0;
    else
       begin
           if(delay_b==16'd49999)
              begin
              delay_1ms<=~delay_1ms;
              delay_b<=16'd0;
              end
           else
              delay_b<=delay_b+1'b1;
       end
end
always@(posedge delay_1s or negedge sys_rstn)
begin
    if(!sys_rstn)
       begin
       num_g<=4'd0;
       num_s<=3'd0;
       end
    else
    begin
       if(num_g==4'd9)
          begin
          num_g<=4'd0;
          num_s<=num_s+1'd1;
          end
       else
          begin
          if(num_g==4'd9&&num_s==3'd5)
             begin
             num_g<=4'd0;
             num_s<=3'd0;
             end
          else
          num_g<=num_g+1'd1;
          end
     end
end

always@(num_g)
      begin
          case(num_g)  
               4'd0: g= 8'hc0;
               4'd1: g= 8'hf9;
               4'd2: g= 8'ha4;
               4'd3: g= 8'hb0;
               4'd4: g= 8'h99;
               4'd5: g= 8'h92;
               4'd6: g= 8'h82;
               4'd7: g= 8'hf8;
               4'd8: g= 8'h80;
               4'd9: g= 8'h90;
          default    g= 8'hc0;
          endcase
      end
always@(num_s)
begin
    case(num_s)
         3'd0: s = 8'hc0;
         3'd1: s = 8'hf9;
         3'd2: s = 8'ha4;
         3'd3: s = 8'hb0;
         3'd4: s = 8'h99;
         3'd5: s = 8'h92;
         default  s=8'hc0;
     endcase
end
always@(delay_1ms)
begin
    if(delay_1ms)
       begin
       sm_seg<=g;
       sm_bit<=8'hfe;
       end
    if(!delay_1ms)
       begin
       sm_seg<=s;
       sm_bit<=8'hfd;
       end
end

endmodule

---

cnt60.rar

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呵呵，刚开始用360的浏览器上传的源码……现在已换了个浏览器更新了。

按键消抖控制2位数码管循环显示0～59

module key_debounce(sys_clk    ,
                    sys_rstn   ,
                    key_in     ,
                    sm_seg     ,
                    sm_bit     


                    );
input               sys_clk    ;
input               sys_rstn   ;
input               key_in     ;
output   [7:0]      sm_seg     ;
output   [7:0]      sm_bit     ;


reg                 key_out    ;
reg      [3:0]      key_cnt    ;
reg      [3:0]      key_cnt_r  ;
reg      [19:0]     delay_cnt  ;
reg      [3:0]      dataout_buf;
reg      [7:0]      sm_seg     ;
wire                key_scan   ;
wire                key_low    ;
reg      [7:0]       sm_bit    ;
reg                 key_samp   ;
reg                 key_samp_r ;
reg                 key_rst    ;
reg                 key_rst_r  ;
reg      [7:0]      g;
reg      [7:0]      s;
reg      [15:0]     delay_b;
reg                 delay_1ms;






always@(posedge sys_clk or negedge sys_rstn)
       begin
           if(!sys_rstn)
              key_samp<=1'b1;
           else
              key_samp<=key_in;
       end
always@(posedge sys_clk or negedge sys_rstn)
       begin
           if(!sys_rstn)
              key_samp_r<=1'b1;
           else
              key_samp_r<=key_samp;
       end
assign key_scan=key_samp_r&(~key_samp);
always@(posedge sys_clk or negedge sys_rstn)
       begin
           if(!sys_rstn)
              delay_cnt<=20'h0;
           else if(key_scan)
                  delay_cnt<=20'h0;
                else
                  delay_cnt<=delay_cnt+1'b1;
       end
always@(posedge sys_clk or negedge sys_rstn)
       begin
           if(!sys_rstn)
              key_rst<=1'b1;
           else
              if(delay_cnt==20'hf4240)
                 key_rst<=key_in;
       end
always@(posedge sys_clk or negedge sys_rstn)
       begin
           if(!sys_rstn)
              key_rst_r<=1'b1;
           else
              key_rst_r<=key_rst;
        end
assign key_low=key_rst_r&(~key_rst);
always@(posedge key_low or negedge sys_rstn )
       begin
           if(!sys_rstn)
              begin
              key_cnt<=4'd0;
              key_cnt_r<=4'd0;
              end
           else
              begin
                  if(key_cnt==4'd9)
                     begin
                     key_cnt<=4'd0;
                     key_cnt_r<=key_cnt_r+1'd1;
                     end
                  else
                     begin
                        if(key_cnt==4'd9&&key_cnt_r==4'd5)
                           begin
                           key_cnt<=4'd0;
                           key_cnt_r<=4'd0;
                           end
                        else
                           key_cnt<=key_cnt+1'b1;
                     end
               end
        end


always@(posedge sys_clk or negedge sys_rstn)
       begin
           if(!sys_rstn)
              delay_1ms<=1'b0;
           else
              begin
                  if(delay_b==16'd49999)
                    begin
                    delay_1ms<=~delay_1ms;
                    delay_b<=16'd0;
                    end
                  else
                    delay_b<=delay_b+1'b1;
              end
        end
always@(key_cnt)
       begin
           case(key_cnt)
               4'd0:g=8'hc0;
               4'd1:g=8'hf9;
               4'd2:g=8'ha4;
               4'd3:g=8'hb0;
               4'd4:g=8'h99;
               4'd5:g=8'h92;
               4'd6:g=8'h82;
               4'd7:g=8'hf8;
               4'd8:g=8'h80;
               4'd9:g=8'h90;
               default:
                    g=8'hc0;
           endcase
       end
always@(key_cnt_r)
       begin
           case(key_cnt_r)
               4'd0:s=8'hc0;
               4'd1:s=8'hf9;
               4'd2:s=8'ha4;
               4'd3:s=8'hb0;
               4'd4:s=8'h99;
               4'd5:s=8'h92;
               default:
                    s=8'hc0;
           endcase
       end
always@(delay_1ms)
       begin
           if(delay_1ms)
             begin
                 sm_seg<=g;
                 sm_bit<=8'hfe;
             end
           if(!delay_1ms)
              begin
                  sm_seg<=s;
                  sm_bit<=8'hfd;
              end
       end
endmodule

实现LCD1602显示两行字母或数字从左向右滚动

module lcd1602(sys_clk    ,

  sys_rstn   ,
  lcd_rs     ,
  lcd_rw     ,
  lcd_en     ,
  lcd_data
  );


input          sys_clk    ;
input          sys_rstn   ;
output         lcd_rs     ;
output         lcd_rw     ;
output         lcd_en     ;
output  [7:0]  lcd_data   ;


reg            lcd_rs     ;
reg            clk_div    ;
reg     [17:0] delay_cnt  ;
reg     [7:0]  lcd_data   ;
reg     [4:0]  char_cnt   ;
reg     [7:0]  data_disp  ;
reg     [9:0]  state      ;   
parameter   idle = 10'b000000000,
  clear = 10'b000000001,
  set_function = 10'b000000010,
  switch_mode = 10'b000000100,
  set_mode     = 10'b000001000,
  shift   = 10'b000010000,
  set_ddram1   = 10'b000100000,
  set_ddram2   = 10'b001000000,
  write_ram1   = 10'b010000000,
  write_ram2   = 10'b100000000;


assign lcd_rw = 1'b0;
assign lcd_en = clk_div;


always@(posedge sys_clk or negedge sys_rstn)
begin 
if(!sys_rstn)
begin
delay_cnt<=18'd0;
clk_div<=1'b0;
end
else if(delay_cnt==18'd249999)
begin
delay_cnt<=18'd0;
clk_div<=~clk_div;
end
else
begin
delay_cnt<=delay_cnt+1'b1;
clk_div<=clk_div;
end
end
always@(posedge clk_div or negedge sys_rstn)
begin
if(!sys_rstn)
begin
state <= idle;
lcd_data <= 8'bzzzzzzzz;
char_cnt <= 5'd0;
end
else
begin
case(state)
idle: begin
state <= clear;
lcd_data <= 8'bzzzzzzzz;
end
clear: begin
state <= set_function;
lcd_rs<=1'b0;
lcd_data <= 8'b00000001;
end
set_function:
begin
state <= switch_mode;
lcd_rs<=1'b0;
lcd_data <= 8'b00111000;
end
switch_mode:
begin
state <= set_mode;
lcd_rs<=1'b0;
lcd_data <= 8'b00001111;
end
set_mode:begin
state <= shift;
lcd_rs<=1'b0;
lcd_data <= 8'b00000110;
end
shift: begin
state <= set_ddram1;
lcd_rs<=1'b0;
lcd_data <= 8'b0001_1100;
end
set_ddram1:    
begin
state <= write_ram1; 
lcd_rs<=1'b0;
lcd_data <= 8'b1000_0000;
end
set_ddram2:
begin
state <= write_ram2;
lcd_rs<=1'b0;
lcd_data <= 8'b1100_0000;
end
write_ram1:
begin
if(char_cnt <=5'd15)
begin
char_cnt <= char_cnt + 1'b1; 
lcd_rs<=1'b1;
lcd_data <= data_disp;
state <= write_ram1;
end
else
begin
state <= set_ddram2;
end
end
write_ram2:
begin
if(char_cnt <=5'd30)
begin
char_cnt <= char_cnt + 1'b1; 
lcd_rs<=1'b1;
lcd_data <= data_disp;
state <= write_ram2;
end
else
begin
char_cnt <=5'd0;
state <= shift;
end
end
default: state <= idle;
endcase
end
end


always @(char_cnt)
begin
case (char_cnt)
5'd0: data_disp  = 8'b01010111;
5'd1: data_disp  = 8'b01100101;
5'd2: data_disp  = 8'b01101100;
5'd3: data_disp  = 8'b01100011;
5'd4: data_disp  = 8'b01101111;
5'd5: data_disp  = 8'b01101101;
5'd6: data_disp  = 8'b01100101;
5'd7: data_disp  = 8'b00100000;
5'd8: data_disp  = 8'b01110100;
5'd9: data_disp  = 8'b01101111;
5'd10: data_disp = 8'b00100000;
5'd11: data_disp = 8'b01110111;
5'd12: data_disp = 8'b01110111;
5'd13: data_disp = 8'b01110111;
5'd14: data_disp = 8'b00101110;
5'd15: data_disp = 8'b01100101;
5'd16: data_disp = 8'b01100101;
5'd17: data_disp = 8'b01110000;
5'd18: data_disp = 8'b01110111;
5'd19: data_disp = 8'b00101110;
5'd20: data_disp = 8'b01100011;
5'd21: data_disp = 8'b01101111;
5'd22: data_disp = 8'b01101101;
5'd23: data_disp = 8'b00101110;
5'd24: data_disp = 8'b01100011;
5'd25: data_disp = 8'b01101110;
5'd26: data_disp = 8'b00100001;
5'd27: data_disp = 8'b00110001;
5'd28: data_disp = 8'b00110010;
5'd29: data_disp = 8'b00110011;
5'd30: data_disp = 8'b00110100;
5'd31: data_disp = 8'b00110101;
5'd32: data_disp = 8'b00110110;
    default :   data_disp = 8'b00100000;
endcase
end
endmodule

乐曲自动演奏

module key_piano(sys_clk    ,
                 sys_rstn   ,
                 key_in     ,
                 beep);
                 
input               sys_clk      ;
input               sys_rstn     ;
input    [7:0]      key_in       ;
output              beep         ;


reg                 beep         ;
reg      [15:0]     delay_cnt    ;
reg      [15:0]     delay_end    ;
reg      [24:0]     delay_1s     ;
reg      [5:0]      auto         ;


always@(posedge sys_clk or negedge sys_rstn)
begin
    if(!sys_rstn)
       delay_cnt<=16'd0;
    else
       if((delay_cnt==delay_end)&(!(delay_end==16'hffff)))
          begin
              delay_cnt<=16'd0;
              beep<=~beep;
          end
       else
          delay_cnt<=delay_cnt+1'b1;
end
always@(posedge sys_clk or negedge sys_rstn)
begin
     if(!sys_rstn)
        delay_1s<=25'd0;
      else
         begin
             if(delay_1s==25'd24999999)
                delay_1s<=25'd0;
             else
                 delay_1s<=delay_1s+1'd1;
          end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
    if(!sys_rstn)
       auto<=6'd0;
    else
       begin
           if(delay_1s==25'd24999999)
              begin
                  if(auto==6'd38)
                     auto<=6'd0;
                  else
                     auto<=auto+1'b1;
              end
           else
              auto<=auto;
       end
end
always@(posedge sys_clk or negedge sys_rstn)
begin
    case(auto)
         6'd00:delay_end = 16'd47774;//1
         6'd01:delay_end = 16'd42568;//2
         6'd02:delay_end = 16'd37919;//3
         6'd03:delay_end = 16'd47774;//1
         6'd04:delay_end = 16'd65535;
         6'd05:delay_end = 16'd47774;//1
         6'd06:delay_end = 16'd42568;//2
         6'd07:delay_end = 16'd37919;//3
         6'd08:delay_end = 16'd47774;//1
         6'd09:delay_end = 16'd65535;
         6'd10:delay_end = 16'd37919;//3
         6'd11:delay_end = 16'd35791;//4
         6'd12:delay_end = 16'd31888;//5
         6'd13:delay_end = 16'd65535;
         6'd14:delay_end = 16'd37919;//3
         6'd15:delay_end = 16'd35791;//4
         6'd16:delay_end = 16'd31888;//5
         6'd17:delay_end = 16'd65535;
         6'd18:delay_end = 16'd31888;//5
         6'd19:delay_end = 16'd28409;//6
         6'd20:delay_end = 16'd31888;//5
         6'd21:delay_end = 16'd35791;//4
         6'd22:delay_end = 16'd37919;//3
         6'd23:delay_end = 16'd47774;//1
         6'd24:delay_end = 16'd65535;
         6'd25:delay_end = 16'd31888;//5
         6'd26:delay_end = 16'd28409;//6
         6'd27:delay_end = 16'd31888;//5
         6'd28:delay_end = 16'd35791;//4
         6'd29:delay_end = 16'd37919;//3
         6'd30:delay_end = 16'd47774;//1
         6'd31:delay_end = 16'd65535;
         6'd32:delay_end = 16'd47774;//1
         6'd33:delay_end = 16'd31888;//5
         6'd34:delay_end = 16'd47774;//1
         6'd35:delay_end = 16'd65535;
         6'd36:delay_end = 16'd47774;//1
         6'd37:delay_end = 16'd31888;//5
         6'd38:delay_end = 16'd47774;//1
       default:delay_end = 16'd65535;
     endcase
end                      
endmodule