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typedef const struct
{
UNS_32 num_sections;
UNS_32 virt_addr; /* calculate index from this */
UNS_32 phys_addr; /* initialize location @ index w/this */
UNS_32 entry; /* 'or'd' combinations of entry settings;
'or' this with phys_addr */
/* Entry settings:
access_perm, domain, cacheable, write_buffered, descriptor_type
*/
} TT_SECTION_BLOCK;

/*
* This alternate EVB mapping puts:
* SRAM at 0x0, Cacheable and Bufferable
* The same SRAM at 0x10000000, not Cacheable and not Bufferable
* SDRAM bank 0 at 0xC0000000, (see code for C/B state)
* SDRAM bank 1 at 0xC2000000, (see code for C/B state)
* Alternately, SDRAM bank 0 & 1 mapped to 0xD0000000 non-cached &
* non-buffered.
*
* Flash, CPLD, Ethernet Controller, Internal RAM, and Registers
* are all mapped so that their Virtual Addresses are the same as
* their Physical Addresses.
* Flash is mapped as Cacheable but not bufferable. CPLD, Internal
* RAM, Ethernet Controlller and Registers are all mapped as not
* Cacheable, and not Bufferable.
*/
TT_SECTION_BLOCK tt_init_sram_at_0 [] = {
/* 64Mbytes contiguous SDRAM */
{8,0xC0000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC0800000,0xC1000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC1000000,0xC4000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC1800000,0xC5000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC2000000,0xC8000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC2800000,0xC9000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC3000000,0xCC000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0xC3800000,0xCD000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},

{8,0x00000000,0xC0000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x00800000,0xC1000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x01000000,0xC4000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x01800000,0xC5000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x02000000,0xC8000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x02800000,0xC9000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x03000000,0xCC000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},
{8,0x03800000,0xCD000000,
L1D_AP_ALL | L1D_DOMAIN(0) | L1D_CACHEABLE | L1D_BUFFERABLE |
L1D_TYPE_SECTION},

/* Flash 1*/
// {4,0x00000000,0xFD000000,
// L1D_AP_ALL | L1D_DOMAIN(8) | //L1D_CACHEABLE |
// L1D_TYPE_SECTION},
{1,0x20000000,0x20000000,
L1D_AP_ALL | L1D_DOMAIN(8) | //L1D_CACHEABLE |
L1D_TYPE_SECTION},
/* Flash 2 */
//{16,0x01000000,0x10000000,
// L1D_AP_ALL | L1D_DOMAIN(9) | L1D_CACHEABLE | L1D_BUFFERABLE |
// L1D_TYPE_SECTION},
/* CPLD */
//{1,0x20000000,0x20000000,
// L1D_AP_ALL | L1D_DOMAIN(11) |
// L1D_TYPE_SECTION},
/* Ethernet Controller on I/O board,
mapped back to its physical address */
//{1,0x30000000,0x30000000,
// L1D_AP_ALL | L1D_DOMAIN(12) |
// L1D_TYPE_SECTION},
/* Internal RAM */
{1,0xB0000000,0xB0000000,
L1D_AP_ALL | L1D_DOMAIN(13) | L1D_TYPE_SECTION},
/* System Registers */
{1,0x80000000,0x80000000,
L1D_AP_ALL | L1D_DOMAIN(14) |
L1D_TYPE_SECTION},
{256,0x40000000,0x40000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
{16,0x50000000,0x00000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
{16,0x51000000,0x10000000,
L1D_AP_ALL | L1D_DOMAIN(13) |
L1D_TYPE_SECTION},
{0,0,0,0} /* Marks end of initialization array */
};

对tt_init_sram_at_0结构初始化中，为何物理地址(第三项phys_addr),如0xC0000000,0xC1000000,0xC4000000,0xC5000000等不是连续的??
(注板子配置为arm9处理器LH7A400，64M字节SDRAM，起始地址为0xC0000000)。相关资料与我联系qq:12966352