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AT91RM9200 关于AT91RM9200的地址线怪现象

问
诸位好,
目前我手上一块RM9200的板子,运行时高位的A25和A23都是有正常波形的,
但独独A24一直是低电平,目前明确是没有短路的。
系统的软件为linux,地址映射到片选7---CS7的空间:0X80000000 开始的256M空间。
请高手指点一下,问题可能出现在哪里,谢谢。 答 1: 非常抱歉,这是芯片的一个BUG,请参考datasheet Page66341.1 EBI
41.1.1 A24 not wired internally between the EBI and the PIO
A24 is not wired internally between the EBI and the PIO. Use only PIO mode on it.
Problem Fix/Workaround
Due to this error, static memories over 16M bytes per chip select CANnot be used. To interface
32-Mbyte memories and over, the user must use two memory chips connected on two different
chip selects. 答 2: 商家都有闻过饰非的习惯,ATMEL也不能免俗这是Atmel论坛上摘下来的,可以解释你的疑问
comma
Joined: 06 Nov 2005
Posts: 2
Posted: 2005-11-06, 9:55 Post subject: large size SDRAM problem?
--------------------------------------------------------------------------------
Im designing my first at91rm9200 board. I want to increase the SDRAM size up to 128MB(64MBx2chip).
in at91rm9200 datasheet, it only support that SDRAM CAS latency is 2. I want select the SAMSUNG K4S511632B-TC(L)75. but in its datasheet tell it CAN support CAS latency 2 & 3.
my question is CAN it be used and whether I must config the SDRAM controller or not?
best regards,
comma
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seismic
Joined: 22 Sep 2004
Posts: 12
Posted: 2005-11-23, 12:39 Post subject: no
--------------------------------------------------------------------------------
9200's max SDRAM size is 64M
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tagmaster.com
Joined: 05 Jul 2005
Posts: 4
Posted: 2005-12-07, 16:59 Post subject: And nasty HW bug
--------------------------------------------------------------------------------
and the chip have a bug, I think it is address pin #25 that is not connected to the silicon during the bonding. You will have a hole in the memory or you have to fix adressing with software. I guess software solutions will slow it down!? So more memory than 32 MB means some patches.
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comma
Joined: 06 Nov 2005
Posts: 2
Posted: 2005-12-11, 10:01 Post subject:
--------------------------------------------------------------------------------
thank you for reminding me. but so stupid mistake CAN occured by atmel?
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PETN
Joined: 26 Nov 2005
Posts: 6
Posted: 2005-12-18, 15:26 Post subject:
--------------------------------------------------------------------------------
Hi
The bug on the silicon does not affect SDRAM interface. It's a problem only if you are using large static devices like nor flash or large (and expensive!) banks of static ram...
Bye
Nicola
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JamesKosin
Joined: 09 Mar 2006
Posts: 19
Location: Newport News, VA
Posted: 2006-03-14, 11:12 Post subject: Re: no
--------------------------------------------------------------------------------
seismic wrote:
9200's max SDRAM size is 64M
Not true... If you read the data sheet, the largest is 256M. You just have to setup the SDRAMC registers correctly to tell it how many row/col address signals are needed.
4-64x8 is 256MB.
答 3: 芯片bug内部的A24没有连接到外部A24引脚上 答 4: 我靠,这也行....这么大的BUG也不出修订版IC。. 答 5: 多谢各位的解答,这个BUG也太离谱了 答 6: 请问你说的ATMEL论坛是他们公司的网站上的吗。
目前我手上一块RM9200的板子,运行时高位的A25和A23都是有正常波形的,
但独独A24一直是低电平,目前明确是没有短路的。
系统的软件为linux,地址映射到片选7---CS7的空间:0X80000000 开始的256M空间。
请高手指点一下,问题可能出现在哪里,谢谢。 答 1: 非常抱歉,这是芯片的一个BUG,请参考datasheet Page66341.1 EBI
41.1.1 A24 not wired internally between the EBI and the PIO
A24 is not wired internally between the EBI and the PIO. Use only PIO mode on it.
Problem Fix/Workaround
Due to this error, static memories over 16M bytes per chip select CANnot be used. To interface
32-Mbyte memories and over, the user must use two memory chips connected on two different
chip selects. 答 2: 商家都有闻过饰非的习惯,ATMEL也不能免俗这是Atmel论坛上摘下来的,可以解释你的疑问
comma
Joined: 06 Nov 2005
Posts: 2
Posted: 2005-11-06, 9:55 Post subject: large size SDRAM problem?
--------------------------------------------------------------------------------
Im designing my first at91rm9200 board. I want to increase the SDRAM size up to 128MB(64MBx2chip).
in at91rm9200 datasheet, it only support that SDRAM CAS latency is 2. I want select the SAMSUNG K4S511632B-TC(L)75. but in its datasheet tell it CAN support CAS latency 2 & 3.
my question is CAN it be used and whether I must config the SDRAM controller or not?
best regards,
comma
Back to top
seismic
Joined: 22 Sep 2004
Posts: 12
Posted: 2005-11-23, 12:39 Post subject: no
--------------------------------------------------------------------------------
9200's max SDRAM size is 64M
Back to top
tagmaster.com
Joined: 05 Jul 2005
Posts: 4
Posted: 2005-12-07, 16:59 Post subject: And nasty HW bug
--------------------------------------------------------------------------------
and the chip have a bug, I think it is address pin #25 that is not connected to the silicon during the bonding. You will have a hole in the memory or you have to fix adressing with software. I guess software solutions will slow it down!? So more memory than 32 MB means some patches.
Back to top
comma
Joined: 06 Nov 2005
Posts: 2
Posted: 2005-12-11, 10:01 Post subject:
--------------------------------------------------------------------------------
thank you for reminding me. but so stupid mistake CAN occured by atmel?
Back to top
PETN
Joined: 26 Nov 2005
Posts: 6
Posted: 2005-12-18, 15:26 Post subject:
--------------------------------------------------------------------------------
Hi
The bug on the silicon does not affect SDRAM interface. It's a problem only if you are using large static devices like nor flash or large (and expensive!) banks of static ram...
Bye
Nicola
Back to top
JamesKosin
Joined: 09 Mar 2006
Posts: 19
Location: Newport News, VA
Posted: 2006-03-14, 11:12 Post subject: Re: no
--------------------------------------------------------------------------------
seismic wrote:
9200's max SDRAM size is 64M
Not true... If you read the data sheet, the largest is 256M. You just have to setup the SDRAMC registers correctly to tell it how many row/col address signals are needed.
4-64x8 is 256MB.
答 3: 芯片bug内部的A24没有连接到外部A24引脚上 答 4: 我靠,这也行....这么大的BUG也不出修订版IC。. 答 5: 多谢各位的解答,这个BUG也太离谱了 答 6: 请问你说的ATMEL论坛是他们公司的网站上的吗。
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